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Fix typo #337

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merged 2 commits into from
Jan 2, 2024
Merged

Fix typo #337

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156d589
Fix typo
HotMercury Dec 25, 2023
fe1a3f3
Fix typo
HotMercury Dec 25, 2023
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8 changes: 4 additions & 4 deletions src/cachesim/cachesim.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ void CacheSim::updateCacheLineReplFields(CacheLine &line, unsigned wayIdx) {
// Find previous LRU value for the updated index
const unsigned preLRU = line[wayIdx].lru;

// All indicies which are curently more recent than preLRU shall be
// All indicies which are currently more recent than preLRU shall be
// incremented
for (auto &set : line) {
if (set.second.valid && set.second.lru < preLRU) {
Expand All @@ -58,7 +58,7 @@ void CacheSim::revertCacheLineReplFields(CacheLine &line,
const CacheWay &oldWay,
unsigned wayIdx) {
if (getReplacementPolicy() == ReplPolicy::LRU) {
// All indicies which are curently less than or equal to the old LRU shall
// All indicies which are currently less than or equal to the old LRU shall
// be decremented
for (auto &set : line) {
if (set.second.valid && set.second.lru <= oldWay.lru) {
Expand Down Expand Up @@ -242,7 +242,7 @@ void CacheSim::analyzeCacheAccess(CacheTransaction &transaction) const {

void CacheSim::pushAccessTrace(const CacheTransaction &transaction) {
// Access traces are pushed in sorted order into the access trace map; indexed
// by a key corresponding to the cycle of the acces.
// by a key corresponding to the cycle of the access.
const unsigned currentCycle =
ProcessorHandler::getProcessor()->getCycleCount();

Expand Down Expand Up @@ -374,7 +374,7 @@ void CacheSim::undo() {
Q_ASSERT(m_cacheLines.at(lineIdx).count(wayIdx) != 0);
way = CacheWay();
}
// Case 2: A miss occured on a valid entry. In this case, we have to restore
// Case 2: A miss occurred on a valid entry. In this case, we have to restore
// the old way, which was evicted
// - Restore the old entry which was evicted
else if (!trace.transaction.isHit) {
Expand Down