[stm32] Prevent SPI RX FIFO overflow in SPI master

In full duplex mode (only mode supported by SpiMaster), every
transmitted byte will produce a corresponding received byte which is
pushed into the RX FIFO with some delay. The existing TX loop does not
limit outstanding transactions to ensure they will fit within the RX
FIFO. If the SPI PHY transmits a frame while the HAL is in its TX loop,
it will freely push more TX frames until the TX FIFO is full. These
extra frames may overflow the RX FIFO if the HAL hasn't gotten to
popping incoming frames by the time they are received.

This could be solved by checking for the SUSP (suspended to prevent
overflow) during TX or by using the DXP bit to coordinate transactions
instead of TXP/RXP. This commit instead chooses to track the number of
outstanding frames using the existing counters and prevent transmit if
there are more outstanding frames than would fit in the RX FIFO.

This implementation assumes 8-bit/one-byte SPI data size, which is an
existing limitation of the SpiMaster.

src/modm/platform/spi/stm32h7/spi_master.cpp.in

@@ -71,7 +71,7 @@ SpiMaster{{ id }}::transfer(
 	std::size_t txIndex = 0;
 
 	while (rxIndex < length) {
-		while ((txIndex < length) and !Hal::isTxFifoFull()) {
+		while ((txIndex < length) and !Hal::isTxFifoFull() and (txIndex - rxIndex) < Hal::FifoSize) {
 			Hal::write(tx ? tx[txIndex] : 0);
 			++txIndex;
 		}
@@ -110,7 +110,7 @@ SpiMaster{{ id }}::transfer(
 			while (rxIndex < length) {
 		default:
 		{
-				while ((txIndex < length) and !Hal::isTxFifoFull()) {
+				while ((txIndex < length) and !Hal::isTxFifoFull() and (txIndex - rxIndex) < Hal::FifoSize) {
 					Hal::write(tx ? tx[txIndex] : 0);
 					++txIndex;
 				}