Merge pull request timvideos#179 from antmicro/update_submodules

Update submodules

Makefile

@@ -241,7 +241,7 @@ image-flash-py: image
 # This is indicated by a "git submodule status" that does not start with
 # a space (" ").
 #
-LITEX_SUBMODULES=migen litex litedram liteeth litepcie litesata litescope liteusb litevideo
+LITEX_SUBMODULES=migen litex litedram liteeth litepcie litesata litescope litevideo
 litex-submodules: $(addsuffix /.git,$(addprefix third_party/,$(LITEX_SUBMODULES)))
 	@if git submodule status --recursive | grep "^[^ ]" >/dev/null; then \
 		echo ""; \

firmware/bist.c

@@ -19,7 +19,7 @@ static void busy_wait(unsigned int ds)
 {
 	timer0_en_write(0);
 	timer0_reload_write(0);
-	timer0_load_write(SYSTEM_CLOCK_FREQUENCY/10*ds);
+	timer0_load_write(CONFIG_CLOCK_FREQUENCY/10*ds);
 	timer0_en_write(1);
 	timer0_update_value_write(1);
 	while(timer0_value_read()) timer0_update_value_write(1);
@@ -44,7 +44,7 @@ void bist_test(void) {
 			timer0_update_value_write(1);
 			ticks = timer0_value_read();
 			ticks = 0xffffffff - ticks;
-			speed = SYSTEM_CLOCK_FREQUENCY/ticks;
+			speed = CONFIG_CLOCK_FREQUENCY/ticks;
 			speed = test_size*speed/1000000;
 			speed = 8*speed;
 			printf(" / %u Mbps\n", speed);
@@ -66,7 +66,7 @@ void bist_test(void) {
 			timer0_update_value_write(1);
 			ticks = timer0_value_read();
 			ticks = 0xffffffff - ticks;
-			speed = SYSTEM_CLOCK_FREQUENCY/ticks;
+			speed = CONFIG_CLOCK_FREQUENCY/ticks;
 			speed = test_size*speed/1000000;
 			speed = 8*speed;
 			printf(" / %u Mbps\n", speed);

firmware/ci.c

@@ -582,7 +582,7 @@ static void status_service(void)
 {
 	static int last_event;
 
-	if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) {
+	if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) {
 		if(status_enabled) {
 			status_print();
 			wputchar('\n');
@@ -1008,7 +1008,7 @@ static void debug_ddr(void)
 	sdram_controller_bandwidth_update_write(1);
 	nr = sdram_controller_bandwidth_nreads_read();
 	nw = sdram_controller_bandwidth_nwrites_read();
-	f = SYSTEM_CLOCK_FREQUENCY;
+	f = CONFIG_CLOCK_FREQUENCY;
 	burstbits = (2*DFII_NPHASES) << DFII_PIX_DATA_SIZE;
 	rdb = (nr*f >> (24 - log2(burstbits)))/1000000ULL;
 	wrb = (nw*f >> (24 - log2(burstbits)))/1000000ULL;

firmware/encoder.c

@@ -178,7 +178,7 @@ void encoder_service(void) {
 	static int can_start;
 
 	if(encoder_enabled) {
-		if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/encoder_target_fps))
+		if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/encoder_target_fps))
 			can_start = 1;
 		if(can_start & encoder_done()) {
 			encoder_init(encoder_quality);
@@ -191,7 +191,7 @@ void encoder_service(void) {
 			encoder_reader_v_width_write(processor_v_active);
 			encoder_reader_start_write(1);
 		}
-		if(elapsed(&last_fps_event, SYSTEM_CLOCK_FREQUENCY)) {
+		if(elapsed(&last_fps_event, CONFIG_CLOCK_FREQUENCY)) {
 			encoder_fps = frame_cnt;
 			frame_cnt = 0;
 		}

firmware/ethernet.c

@@ -31,8 +31,8 @@ void ethernet_init(const unsigned char * mac_addr, const unsigned char *ip_addr)
 	liteethmac_init();
 
 	/* uip periods */
-	uip_periodic_period = SYSTEM_CLOCK_FREQUENCY/100; /*  10 ms */
-	uip_arp_period = SYSTEM_CLOCK_FREQUENCY/10;       /* 100 ms */
+	uip_periodic_period = CONFIG_CLOCK_FREQUENCY/100; /*  10 ms */
+	uip_arp_period = CONFIG_CLOCK_FREQUENCY/10;       /* 100 ms */
 
 	/* init uip */
 	process_init();

firmware/hdmi_in0.c

@@ -204,7 +204,7 @@ static int wait_idelays(void)
 	while(hdmi_in0_data0_cap_dly_busy_read()
 	  || hdmi_in0_data1_cap_dly_busy_read()
 	  || hdmi_in0_data2_cap_dly_busy_read()) {
-		if(elapsed(&ev, SYSTEM_CLOCK_FREQUENCY >> 6) == 0) {
+		if(elapsed(&ev, CONFIG_CLOCK_FREQUENCY >> 6) == 0) {
 			wprintf("dvisampler0: IDELAY busy timeout (%hhx %hhx %hhx)\n",
 				hdmi_in0_data0_cap_dly_busy_read(),
 				hdmi_in0_data1_cap_dly_busy_read(),
@@ -402,7 +402,7 @@ static int hdmi_in0_clocking_locked_filtered(void)
 				lock_status = 1;
 				break;
 			case 1:
-				if(elapsed(&lock_start_time, SYSTEM_CLOCK_FREQUENCY/4))
+				if(elapsed(&lock_start_time, CONFIG_CLOCK_FREQUENCY/4))
 					lock_status = 2;
 				break;
 			case 2:
@@ -432,7 +432,7 @@ void hdmi_in0_service(int freq)
 		} else {
 			if(hdmi_in0_locked) {
 				if(hdmi_in0_clocking_locked_filtered()) {
-					if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/2)) {
+					if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/2)) {
 						hdmi_in0_adjust_phase();
 						if(hdmi_in0_debug)
 							hdmi_in0_print_status();

firmware/heartbeat.c

@@ -30,7 +30,7 @@ void hb_service(fb_ptrdiff_t fb_offset)
 
 	if (heartbeat_status==1) {
 		hb_fill(color_v, fb_offset);
-		if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY/FILL_RATE)) {
+		if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY/FILL_RATE)) {
 			counter = counter + 1;
 			if(counter > FILL_RATE/(HEARTBEAT_FREQUENCY*2)) {
 				color_v = !color_v;

firmware/oled.c

@@ -42,7 +42,7 @@ static void busy_wait(unsigned int ds)
 {
 	timer0_en_write(0);
 	timer0_reload_write(0);
-	timer0_load_write(SYSTEM_CLOCK_FREQUENCY/100*ds);
+	timer0_load_write(CONFIG_CLOCK_FREQUENCY/100*ds);
 	timer0_en_write(1);
 	timer0_update_value_write(1);
 	while(timer0_value_read()) timer0_update_value_write(1);

firmware/pattern.c

@@ -260,7 +260,7 @@ void pattern_service(void)
 	static int last_event;
 	static char buffer[16];
 
-	if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) {
+	if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) {
 		sprintf(buffer, "Uptime: %s", uptime_str());
 		pattern_draw_text(1, 1, buffer);
 	}

firmware/uip/clock-arch.c

@@ -21,7 +21,7 @@ clock_time_t clock_time(void)
 	unsigned int prescaler;
 	clock_time_t ticks;
 
-	freq = SYSTEM_CLOCK_FREQUENCY;
+	freq = CONFIG_CLOCK_FREQUENCY;
 	prescaler = freq/CLOCK_CONF_SECOND;
 	timer0_update_value_write(1);
 	ticks = (0xffffffff - timer0_value_read())/prescaler;

firmware/uptime.c

@@ -13,7 +13,7 @@ void uptime_service(void)
 {
 	static int last_event;
 
-	if(elapsed(&last_event, SYSTEM_CLOCK_FREQUENCY)) {
+	if(elapsed(&last_event, CONFIG_CLOCK_FREQUENCY)) {
 		uptime_seconds++;
 	}
 }

scripts/settings.sh

@@ -31,6 +31,5 @@ LITE_REPOS="
 	litepcie
 	litesata
 	litescope
-	liteusb
 	litevideo
 	"

targets/arty/base.py

@@ -112,6 +112,13 @@ class BaseSoC(SoCSDRAM):
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
+    SoCSDRAM.mem_map = {
+        "rom":      0x00000000,  # (default shadow @0x80000000)
+        "sram":     0x10000000,  # (default shadow @0x90000000)
+        "main_ram": 0x40000000,  # (default shadow @0xc0000000)
+        "csr":      0x60000000,  # (default shadow @0xe0000000)
+    }
+
     mem_map = {
         "spiflash": 0x20000000,  # (default shadow @0xa0000000)
     }