Musvit

A FPGA friendly dynamic multiple issue RISC-V processor written in Chisel. The name of the processor is Musvit which is the Danish word for the bird great tit.

Dependencies

This project assumes a Unix like operating system. Make sure you have the following dependencies installed.

For development

• SBT
• JDK
• RISC-V toolchain

For synthesis

• Firtool
• F4PGA

Nix users

If you use the Nix package manager you can use the Flake provided in this repository to install all dependencies in a development environment:

nix develop

Configuring Musvit

The configuration of Musvit is defined in src/main/scala/musvit/MusvitConfig.scala:

case class MusvitConfig(
    issueWidth: Int = 2,            // Number of instructions issued per cycle
    romFile: String = "",           // File with ROM contents
    romSize: Int = 0x00001000,      // ROM size in bytes
    romAddr: Long = 0x00000000L,    // Start address of ROM
    resetPC: Long = 0x00000000L,    // Initial PC value
    clockFrequency: Int = -1,       // Clock frequency of Musvit
    ramSize: Int = 0x00001000,      // RAM size in bytes
    ramAddr: Long = 0x00001000L,    // Start address of RAM
    instQueueEntries: Int = 8,      // Number of entries in instruction queue
    robEntries: Int = 16,           // Number of entries in ROB
    btbEntries: Int = 8,            // Number of entries in BTB
    aluNum: Int = 2,                // Number of ALU units
    mulNum: Int = 1,                // Number of multiply units
    divNum: Int = 1,                // Number of division units
    lsuNum: Int = 2,                // Number of load store units
)

Options for configuring make targets can be specified in a config.mk file. An example could be:

# For generating Musvit
APPTARGET=fibonacci-fpga
BOARD=basys3
CLOCKFREQ=100000000

# Testing stuff
TESTTARGET=musvit.MusvitCoreTester
WAVETARGET=test_run_dir/MusvitCore_should_pass/MusvitCore.vcd # This file is generated by the test
WAVECONFIG=musvit-core.gtkw # This file is created by the user

Running tests

To run all tests do:

make testall

To run the test specified in config.mk do:

make test

Some of the tests require a binary file obtained from the software directory. To compile all software do:

make -C sw/

Note that on some systems the RISC-V toolchain prefix needs to be changed. This can be done a sw/config.mk and the prefix could for exampel be set to TOOLCHAIN_PREFIX=riscv64-linux-gnu-.

To quickly see waveforms from a test do:

make wave

or test and waveforms in one command:

make test wave

Generating SystemVerilog from Chisel

Most synthesis tools accepts less abstract HDLs like SystemVerilog. This means the Chisel code needs to be converted to SystemVerilog representation in order to synthesize it. This can be done with the command:

make rtl

This will create a directory called rtl/ where the SystemVerilog files are located.

Synthesizing Musvit

Musvit can be synthesized and programmed to a Basys 3 with the open source tool chain F4PGA. The F4PGA needs to be installed locally. I have a another repository with an installation guide. When the tools are installed create the file synth/basys3/config.mk where the installation path is specified. Mine looks like this:

F4PGA_INSTALL_DIR  ?= /home/madsrumlenordstrom/repos/f4pga/tools
F4PGA_EXAMPLES_DIR ?= /home/madsrumlenordstrom/repos/f4pga/f4pga-examples

To synthesize the design run:

make synth

This will take some time but will generate the bitstream required for programming the FPGA.

When the bitstream has been generated plug in your Basys 3 with a USB cable and run:

make program

You should now see your FPGA calculating fibonacci numbers if the example config.mk is used.