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Rebase, carry over the EEW check added in llvm#101152
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Since we don't have access to the MVTs, we can also do the same thing by checking the VLMAXs are the same (i.e. the sew/lmul ratio)
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lukel97 committed Aug 5, 2024
1 parent 957d7f5 commit a621896
Showing 1 changed file with 10 additions and 0 deletions.
10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -373,6 +373,12 @@ lookupActiveElementsAffectsResult(const MachineInstr &MI) {
return Info->ActiveElementsAffectResult;
}

static unsigned getSEWLMULRatio(const MachineInstr &MI) {
RISCVII::VLMUL LMUL = RISCVII::getLMul(MI.getDesc().TSFlags);
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
return RISCVVType::getSEWLMULRatio(1 << Log2SEW, LMUL);
}

/// If a PseudoVMV_V_V is the only user of its input, fold its passthru and VL
/// into it.
///
Expand All @@ -399,6 +405,10 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
!RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags))
return false;

// Src needs to have the same VLMAX as MI
if (getSEWLMULRatio(MI) != getSEWLMULRatio(*Src))
return false;

// Src needs to have the same passthru as VMV_V_V
if (Src->getOperand(1).getReg() != RISCV::NoRegister &&
Src->getOperand(1).getReg() != Passthru.getReg())
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