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[rv_dm,dv] Avoid a fast JTAG clock #23363

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merged 2 commits into from
May 30, 2024
Merged

[rv_dm,dv] Avoid a fast JTAG clock #23363

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d6e1599
[rv_dm,dv] Increase timeout for CSR tests
rswarbrick May 29, 2024
d425a26
[rv_dm,dv] Avoid a fast JTAG clock
rswarbrick May 29, 2024
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6 changes: 3 additions & 3 deletions hw/ip/rv_dm/dv/env/seq_lib/rv_dm_base_vseq.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ class rv_dm_base_vseq extends cip_base_vseq #(
rand int unsigned tck_period_ps;
constraint tck_period_ps_c {
tck_period_ps dist {
[10_000:20_000] :/ 1, // 50-100MHz
[20_001:42_000] :/ 1, // 24-50MHz
[42_001:100_000] :/ 1 // 10-24MHz
[100_000:200_000] :/ 1, // 5-10MHz
[200_001:420_000] :/ 1, // 2.4-5MHz
[420_001:1000_000] :/ 1 // 1-2.4MHz
};
}

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15 changes: 15 additions & 0 deletions hw/ip/rv_dm/dv/env/seq_lib/rv_dm_common_vseq.sv
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Expand Up @@ -22,6 +22,21 @@ class rv_dm_common_vseq extends rv_dm_base_vseq;
unavailable == 0;
}

// This is a thin wrapper around the base class version of run_csr_vseq, but setting the timeout
// for the CSR operations to be larger. This is needed because the timeout counts from (roughly)
// the start of the CSR sequence and isn't enough to allow for slow values of the JTAG clock.
virtual task run_csr_vseq(string csr_test_type,
int num_test_csrs = 0,
bit do_rand_wr_and_reset = 1,
dv_base_reg_block models[$] = {},
string ral_name = "");
uint old_dtn = csr_utils_pkg::default_timeout_ns;

csr_utils_pkg::default_timeout_ns = 10 * old_dtn;
super.run_csr_vseq(csr_test_type, num_test_csrs, do_rand_wr_and_reset, models, ral_name);
csr_utils_pkg::default_timeout_ns = old_dtn;
endtask

virtual task body();
run_common_vseq_wrapper(num_trans);
endtask : body
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