[LoongArch] Remove spurious mask operations from andn->icmp on 16 and 8 bit values #99272
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@llvm/pr-subscribers-backend-loongarch Author: hev (heiher) ChangesFull diff: https://github.com/llvm/llvm-project/pull/99272.diff 2 Files Affected:
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 79da36c03e304..45829762563fa 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -335,6 +335,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::SRL);
+ setTargetDAGCombine(ISD::SETCC);
// Set DAG combine for 'LSX' feature.
@@ -2528,6 +2529,165 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+static bool checkValueWidth(SDValue V, ISD::LoadExtType &ExtType) {
+ ExtType = ISD::NON_EXTLOAD;
+
+ switch (V.getNode()->getOpcode()) {
+ case ISD::LOAD: {
+ LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
+ if ((LoadNode->getMemoryVT() == MVT::i8) ||
+ (LoadNode->getMemoryVT() == MVT::i16)) {
+ ExtType = LoadNode->getExtensionType();
+ return true;
+ }
+ return false;
+ }
+ case ISD::AssertSext: {
+ VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
+ if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
+ ExtType = ISD::SEXTLOAD;
+ return true;
+ }
+ return false;
+ }
+ case ISD::AssertZext: {
+ VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
+ if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
+ ExtType = ISD::ZEXTLOAD;
+ return true;
+ }
+ return false;
+ }
+ default:
+ return false;
+ }
+
+ return false;
+}
+
+// Eliminate redundant truncation and zero-extension nodes.
+// * Case 1:
+// +------------+ +------------+ +------------+
+// | Input1 | | Input2 | | CC |
+// +------------+ +------------+ +------------+
+// | | |
+// V V +----+
+// +------------+ +------------+ |
+// | TRUNCATE | | TRUNCATE | |
+// +------------+ +------------+ |
+// | | |
+// V V |
+// +------------+ +------------+ |
+// | ZERO_EXT | | ZERO_EXT | |
+// +------------+ +------------+ |
+// | | |
+// | +-------------+ |
+// V V | |
+// +----------------+ | |
+// | AND | | |
+// +----------------+ | |
+// | | |
+// +---------------+ | |
+// | | |
+// V V V
+// +-------------+
+// | CMP |
+// +-------------+
+// * Case 2:
+// +------------+ +------------+ +-------------+ +------------+ +------------+
+// | Input1 | | Input2 | | Constant -1 | | Constant 0 | | CC |
+// +------------+ +------------+ +-------------+ +------------+ +------------+
+// | | | | |
+// V | | | |
+// +------------+ | | | |
+// | XOR |<---------------------+ | |
+// +------------+ | | |
+// | | | |
+// V V +---------------+ |
+// +------------+ +------------+ | |
+// | TRUNCATE | | TRUNCATE | | +-------------------------+
+// +------------+ +------------+ | |
+// | | | |
+// V V | |
+// +------------+ +------------+ | |
+// | ZERO_EXT | | ZERO_EXT | | |
+// +------------+ +------------+ | |
+// | | | |
+// V V | |
+// +----------------+ | |
+// | AND | | |
+// +----------------+ | |
+// | | |
+// +---------------+ | |
+// | | |
+// V V V
+// +-------------+
+// | CMP |
+// +-------------+
+static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const LoongArchSubtarget &Subtarget) {
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+
+ SDNode *AndNode = N->getOperand(0).getNode();
+ if (AndNode->getOpcode() != ISD::AND)
+ return SDValue();
+
+ SDValue AndInputValue2 = AndNode->getOperand(1);
+ if (AndInputValue2.getOpcode() != ISD::ZERO_EXTEND)
+ return SDValue();
+
+ SDValue CmpInputValue = N->getOperand(1);
+ SDValue AndInputValue1 = AndNode->getOperand(0);
+ if (AndInputValue1.getOpcode() == ISD::XOR) {
+ if (CC != ISD::SETEQ && CC != ISD::SETNE)
+ return SDValue();
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndInputValue1.getOperand(1));
+ if (!CN || CN->getSExtValue() != -1)
+ return SDValue();
+ CN = dyn_cast<ConstantSDNode>(CmpInputValue);
+ if (!CN || CN->getSExtValue() != 0)
+ return SDValue();
+ AndInputValue1 = AndInputValue1.getOperand(0);
+ if (AndInputValue1.getOpcode() != ISD::ZERO_EXTEND)
+ return SDValue();
+ } else if (AndInputValue1.getOpcode() == ISD::ZERO_EXTEND) {
+ if (AndInputValue2 != CmpInputValue)
+ return SDValue();
+ } else {
+ return SDValue();
+ }
+
+ SDValue TruncValue1 = AndInputValue1.getNode()->getOperand(0);
+ if (TruncValue1.getOpcode() != ISD::TRUNCATE)
+ return SDValue();
+
+ SDValue TruncValue2 = AndInputValue2.getNode()->getOperand(0);
+ if (TruncValue2.getOpcode() != ISD::TRUNCATE)
+ return SDValue();
+
+ SDValue TruncInputValue1 = TruncValue1.getNode()->getOperand(0);
+ SDValue TruncInputValue2 = TruncValue2.getNode()->getOperand(0);
+ ISD::LoadExtType ExtType1;
+ ISD::LoadExtType ExtType2;
+
+ if (!checkValueWidth(TruncInputValue1, ExtType1) ||
+ !checkValueWidth(TruncInputValue2, ExtType2))
+ return SDValue();
+
+ if ((ExtType2 != ISD::ZEXTLOAD) &&
+ ((ExtType2 != ISD::SEXTLOAD) && (ExtType1 != ISD::SEXTLOAD)))
+ return SDValue();
+
+ // These truncation and zero-extension nodes are not necessary, remove them.
+ SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0),
+ TruncInputValue1, TruncInputValue2);
+ SDValue NewSetCC =
+ DAG.getSetCC(SDLoc(N), N->getValueType(0), NewAnd, TruncInputValue2, CC);
+ DAG.ReplaceAllUsesWith(N, NewSetCC.getNode());
+ return SDValue(N, 0);
+}
+
// Combine (loongarch_bitrev_w (loongarch_revb_2w X)) to loongarch_bitrev_4b.
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
@@ -3155,6 +3315,8 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
return performANDCombine(N, DAG, DCI, Subtarget);
case ISD::OR:
return performORCombine(N, DAG, DCI, Subtarget);
+ case ISD::SETCC:
+ return performSETCCCombine(N, DAG, DCI, Subtarget);
case ISD::SRL:
return performSRLCombine(N, DAG, DCI, Subtarget);
case LoongArchISD::BITREV_W:
diff --git a/llvm/test/CodeGen/LoongArch/andn-icmp.ll b/llvm/test/CodeGen/LoongArch/andn-icmp.ll
index 4fc3c8df4664c..6d07e7a947297 100644
--- a/llvm/test/CodeGen/LoongArch/andn-icmp.ll
+++ b/llvm/test/CodeGen/LoongArch/andn-icmp.ll
@@ -6,14 +6,12 @@ define i1 @andn_icmp_eq_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_eq_i8:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
-; LA32-NEXT: andi $a0, $a0, 255
; LA32-NEXT: sltui $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_eq_i8:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
-; LA64-NEXT: andi $a0, $a0, 255
; LA64-NEXT: sltui $a0, $a0, 1
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -25,14 +23,12 @@ define i1 @andn_icmp_eq_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_eq_i16:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
-; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
; LA32-NEXT: sltui $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_eq_i16:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
-; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
; LA64-NEXT: sltui $a0, $a0, 1
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -80,14 +76,12 @@ define i1 @andn_icmp_ne_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ne_i8:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
-; LA32-NEXT: andi $a0, $a0, 255
; LA32-NEXT: sltu $a0, $zero, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ne_i8:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
-; LA64-NEXT: andi $a0, $a0, 255
; LA64-NEXT: sltu $a0, $zero, $a0
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -99,14 +93,12 @@ define i1 @andn_icmp_ne_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ne_i16:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
-; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
; LA32-NEXT: sltu $a0, $zero, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ne_i16:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
-; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
; LA64-NEXT: sltu $a0, $zero, $a0
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -153,15 +145,13 @@ define i1 @andn_icmp_ne_i64(i64 %a, i64 %b) nounwind {
define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ult_i8:
; LA32: # %bb.0:
-; LA32-NEXT: andi $a1, $a1, 255
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ult_i8:
; LA64: # %bb.0:
-; LA64-NEXT: andi $a1, $a1, 255
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -172,15 +162,13 @@ define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ult_i16:
; LA32: # %bb.0:
-; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ult_i16:
; LA64: # %bb.0:
-; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -191,16 +179,14 @@ define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_uge_i8:
; LA32: # %bb.0:
-; LA32-NEXT: andi $a1, $a1, 255
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_uge_i8:
; LA64: # %bb.0:
-; LA64-NEXT: andi $a1, $a1, 255
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -212,16 +198,14 @@ define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_uge_i16:
; LA32: # %bb.0:
-; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_uge_i16:
; LA64: # %bb.0:
-; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -233,15 +217,13 @@ define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ugt_i8:
; LA32: # %bb.0:
-; LA32-NEXT: andi $a1, $a1, 255
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ugt_i8:
; LA64: # %bb.0:
-; LA64-NEXT: andi $a1, $a1, 255
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -252,15 +234,13 @@ define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ugt_i16:
; LA32: # %bb.0:
-; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ugt_i16:
; LA64: # %bb.0:
-; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -271,16 +251,14 @@ define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ule_i8:
; LA32: # %bb.0:
-; LA32-NEXT: andi $a1, $a1, 255
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ule_i8:
; LA64: # %bb.0:
-; LA64-NEXT: andi $a1, $a1, 255
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -292,16 +270,14 @@ define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ule_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ule_i16:
; LA32: # %bb.0:
-; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
-; LA32-NEXT: and $a0, $a1, $a0
+; LA32-NEXT: and $a0, $a0, $a1
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ule_i16:
; LA64: # %bb.0:
-; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
-; LA64-NEXT: and $a0, $a1, $a0
+; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
|
SixWeining
approved these changes
Jul 17, 2024
|
This change causes some assertion failures when building the Linux kernel. A C reproducer from struct vdpa_config_ops {
char (*get_status)(int *);
} vhost_vdpa_set_status_v_1_0;
unsigned char vhost_vdpa_set_status_status, vhost_vdpa_set_status_status_old;
int vhost_vdpa_set_status_vdpa;
long vhost_vdpa_set_status() {
struct vdpa_config_ops ops = vhost_vdpa_set_status_v_1_0;
vhost_vdpa_set_status_status_old =
ops.get_status(&vhost_vdpa_set_status_vdpa);
if (vhost_vdpa_set_status_status &&
vhost_vdpa_set_status_status_old & ~vhost_vdpa_set_status_status)
return 2;
return 0;
}target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "loongarch64"
define i64 @vhost_vdpa_set_status() #0 {
entry:
%call = tail call signext i8 null(ptr null)
%0 = load i8, ptr null, align 1
%tobool.not = icmp eq i8 %0, 0
br i1 %tobool.not, label %if.end, label %land.lhs.true
land.lhs.true: ; preds = %entry
%conv = zext i8 %0 to i32
%conv1 = zext i8 %call to i32
%not = xor i32 %conv, -1
%and = and i32 %not, %conv1
%tobool3.not = icmp eq i32 %and, 0
br i1 %tobool3.not, label %if.end, label %cleanup
if.end: ; preds = %land.lhs.true, %entry
br label %cleanup
cleanup: ; preds = %if.end, %land.lhs.true
%retval.0 = phi i64 [ 0, %if.end ], [ 1, %land.lhs.true ]
ret i64 %retval.0
}
attributes #0 = { "target-features"="+64bit,+d,+f,+ual" } |
heiher
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Jul 21, 2024
|
@nathanchance Thanks for pointing this out. I'll recommit once it's fixed. |
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sgundapa
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Jul 23, 2024
…n 16 and 8 bit values" (llvm#99792) Reverts llvm#99272
sgundapa
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sgundapa
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… on 16 and 8 bit values" (llvm#99798) recommit of llvm#99272
yuxuanchen1997
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Jul 25, 2024
… 8 bit values (#99272) Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60250930
yuxuanchen1997
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…n 16 and 8 bit values" (#99792) Summary: Reverts #99272 Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251169
yuxuanchen1997
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yuxuanchen1997
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Jul 25, 2024
… on 16 and 8 bit values" (#99798) Summary: recommit of #99272 Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251358
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