Finish deleting the le32/le64 targets #98497
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… targets"" This reverts commit ef5e7f9.
AaronBallman
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@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-clang Author: Aaron Ballman (AaronBallman) ChangesThis is a revert of ef5e7f9 which was a temporary partial revert of 77ac823. The le32 and le64 targets are no longer necessary to retain, so this removes them entirely. Full diff: https://github.com/llvm/llvm-project/pull/98497.diff 17 Files Affected:
diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt
index a8ee8f1fcb87c..62871133a6807 100644
--- a/clang/docs/tools/clang-formatted-files.txt
+++ b/clang/docs/tools/clang-formatted-files.txt
@@ -362,7 +362,6 @@ clang/lib/Basic/Targets/BPF.cpp
clang/lib/Basic/Targets/BPF.h
clang/lib/Basic/Targets/Hexagon.h
clang/lib/Basic/Targets/Lanai.h
-clang/lib/Basic/Targets/Le64.h
clang/lib/Basic/Targets/M68k.h
clang/lib/Basic/Targets/MSP430.h
clang/lib/Basic/Targets/NVPTX.cpp
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index f30680552e0f5..e7ebc8f191aa6 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -102,7 +102,6 @@ add_clang_library(clangBasic
Targets/DirectX.cpp
Targets/Hexagon.cpp
Targets/Lanai.cpp
- Targets/Le64.cpp
Targets/LoongArch.cpp
Targets/M68k.cpp
Targets/MSP430.cpp
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 29133f9ee8fce..0b8e565345b6a 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -23,7 +23,6 @@
#include "Targets/DirectX.h"
#include "Targets/Hexagon.h"
#include "Targets/Lanai.h"
-#include "Targets/Le64.h"
#include "Targets/LoongArch.h"
#include "Targets/M68k.h"
#include "Targets/MSP430.h"
@@ -344,17 +343,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<M68kTargetInfo>(Triple, Opts);
}
- case llvm::Triple::le32:
- switch (os) {
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<PNaClTargetInfo>>(Triple, Opts);
- default:
- return nullptr;
- }
-
- case llvm::Triple::le64:
- return std::make_unique<Le64TargetInfo>(Triple, Opts);
-
case llvm::Triple::ppc:
switch (os) {
case llvm::Triple::Linux:
diff --git a/clang/lib/Basic/Targets/Le64.cpp b/clang/lib/Basic/Targets/Le64.cpp
deleted file mode 100644
index f7afa0e747d67..0000000000000
--- a/clang/lib/Basic/Targets/Le64.cpp
+++ /dev/null
@@ -1,30 +0,0 @@
-//===--- Le64.cpp - Implement Le64 target feature support -----------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements Le64 TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Le64.h"
-#include "Targets.h"
-#include "clang/Basic/Builtins.h"
-#include "clang/Basic/MacroBuilder.h"
-#include "clang/Basic/TargetBuiltins.h"
-
-using namespace clang;
-using namespace clang::targets;
-
-ArrayRef<Builtin::Info> Le64TargetInfo::getTargetBuiltins() const {
- return {};
-}
-
-void Le64TargetInfo::getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
- DefineStd(Builder, "unix", Opts);
- defineCPUMacros(Builder, "le64", /*Tuning=*/false);
-}
diff --git a/clang/lib/Basic/Targets/Le64.h b/clang/lib/Basic/Targets/Le64.h
deleted file mode 100644
index 45f6a4e9dd75d..0000000000000
--- a/clang/lib/Basic/Targets/Le64.h
+++ /dev/null
@@ -1,64 +0,0 @@
-//===--- Le64.h - Declare Le64 target feature support -----------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares Le64 TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H
-#define LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H
-
-#include "clang/Basic/TargetInfo.h"
-#include "clang/Basic/TargetOptions.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/TargetParser/Triple.h"
-
-namespace clang {
-namespace targets {
-
-class LLVM_LIBRARY_VISIBILITY Le64TargetInfo : public TargetInfo {
-
-public:
- Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
- : TargetInfo(Triple) {
- NoAsmVariants = true;
- LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
- resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
- }
-
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override;
-
- ArrayRef<Builtin::Info> getTargetBuiltins() const override;
-
- BuiltinVaListKind getBuiltinVaListKind() const override {
- return TargetInfo::PNaClABIBuiltinVaList;
- }
-
- std::string_view getClobbers() const override { return ""; }
-
- ArrayRef<const char *> getGCCRegNames() const override {
- return std::nullopt;
- }
-
- ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
- return std::nullopt;
- }
-
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- return false;
- }
-
- bool hasProtectedVisibility() const override { return false; }
-};
-
-} // namespace targets
-} // namespace clang
-#endif // LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H
diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h
index 5f27c3469f861..4fcf16c62ae62 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -842,8 +842,8 @@ class LLVM_LIBRARY_VISIBILITY NaClTargetInfo : public OSTargetInfo<Target> {
} else if (Triple.getArch() == llvm::Triple::mipsel) {
// Handled on mips' setDataLayout.
} else {
- assert(Triple.getArch() == llvm::Triple::le32);
- this->resetDataLayout("e-p:32:32-i64:64");
+ assert(Triple.getArch() == llvm::Triple::mipsel);
+ // Handled on mips' setDataLayout.
}
}
};
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 5c810cd332185..e5d6c890134e8 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -116,8 +116,6 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
default:
return createDefaultTargetCodeGenInfo(CGM);
- case llvm::Triple::le32:
- return createPNaClTargetCodeGenInfo(CGM);
case llvm::Triple::m68k:
return createM68kTargetCodeGenInfo(CGM);
case llvm::Triple::mips:
diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp
index e1d056765a866..6e5fa0faf73d7 100644
--- a/clang/lib/CodeGen/ItaniumCXXABI.cpp
+++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp
@@ -576,13 +576,6 @@ CodeGen::CGCXXABI *CodeGen::CreateItaniumCXXABI(CodeGenModule &CGM) {
return new XLCXXABI(CGM);
case TargetCXXABI::GenericItanium:
- if (CGM.getContext().getTargetInfo().getTriple().getArch()
- == llvm::Triple::le32) {
- // For PNaCl, use ARM-style method pointers so that PNaCl code
- // does not assume anything about the alignment of function
- // pointers.
- return new ItaniumCXXABI(CGM, /*UseARMMethodPtrABI=*/true);
- }
return new ItaniumCXXABI(CGM);
case TargetCXXABI::Microsoft:
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index edb3c20ec9768..538a8ca9aa8dd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -3812,12 +3812,6 @@ static void RenderBuiltinOptions(const ToolChain &TC, const llvm::Triple &T,
if (UseBuiltins)
A->render(Args, CmdArgs);
}
-
- // le32-specific flags:
- // -fno-math-builtin: clang should not convert math builtins to intrinsics
- // by default.
- if (TC.getArch() == llvm::Triple::le32)
- CmdArgs.push_back("-fno-math-builtin");
}
bool Driver::getDefaultModuleCachePath(SmallVectorImpl<char> &Result) {
diff --git a/clang/test/CodeGen/bitfield-access-pad.c b/clang/test/CodeGen/bitfield-access-pad.c
index edda7b7798d05..8608c5bd8be11 100644
--- a/clang/test/CodeGen/bitfield-access-pad.c
+++ b/clang/test/CodeGen/bitfield-access-pad.c
@@ -16,7 +16,6 @@
// Configs that have expensive unaligned access
// Little Endian
// RUN: %clang_cc1 -triple=hexagon-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s
-// RUN: %clang_cc1 -triple=le64-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s
// Big endian
// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s
diff --git a/clang/test/CodeGen/bitfield-access-unit.c b/clang/test/CodeGen/bitfield-access-unit.c
index d0553c5183eef..c1b0a43cccc88 100644
--- a/clang/test/CodeGen/bitfield-access-unit.c
+++ b/clang/test/CodeGen/bitfield-access-unit.c
@@ -53,8 +53,8 @@
// RUN: %clang_cc1 -triple=sparc-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT-STRICT %s
// RUN: %clang_cc1 -triple=tce-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT-STRICT %s
-// Both le64-elf and m68-elf are strict alignment ISAs with 4-byte aligned
-// 64-bit or 2-byte aligned 32-bit integer types. This more compex to describe here.
+// m68-elf is a strict alignment ISA with 4-byte aligned 64-bit or 2-byte
+// aligned 32-bit integer types. This more compex to describe here.
// If unaligned access is expensive don't stick these together.
struct A {
diff --git a/clang/test/CodeGenCXX/bitfield-access-empty.cpp b/clang/test/CodeGenCXX/bitfield-access-empty.cpp
index c5e6f55ffa696..96047ce472997 100644
--- a/clang/test/CodeGenCXX/bitfield-access-empty.cpp
+++ b/clang/test/CodeGenCXX/bitfield-access-empty.cpp
@@ -26,7 +26,6 @@
// RUN: %clang_cc1 -triple=bpf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=csky %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=hexagon-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
-// RUN: %clang_cc1 -triple=le64-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=loongarch32-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=nvptx-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=riscv32 %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
diff --git a/clang/test/CodeGenCXX/bitfield-access-tail.cpp b/clang/test/CodeGenCXX/bitfield-access-tail.cpp
index 1539e17cad436..fb961f327f2e5 100644
--- a/clang/test/CodeGenCXX/bitfield-access-tail.cpp
+++ b/clang/test/CodeGenCXX/bitfield-access-tail.cpp
@@ -26,7 +26,6 @@
// RUN: %clang_cc1 -triple=bpf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT64 %s
// RUN: %clang_cc1 -triple=csky %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT32 %s
// RUN: %clang_cc1 -triple=hexagon-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT32 %s
-// RUN: %clang_cc1 -triple=le64-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT64 %s
// RUN: %clang_cc1 -triple=loongarch32-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT32 %s
// RUN: %clang_cc1 -triple=nvptx-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT32 %s
// RUN: %clang_cc1 -triple=riscv32 %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT,LAYOUT32 %s
diff --git a/clang/test/Preprocessor/predefined-macros-no-warnings.c b/clang/test/Preprocessor/predefined-macros-no-warnings.c
index 722e3e77214b6..d44b99a2b192a 100644
--- a/clang/test/Preprocessor/predefined-macros-no-warnings.c
+++ b/clang/test/Preprocessor/predefined-macros-no-warnings.c
@@ -75,8 +75,6 @@
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple m68k
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple m68k-linux
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple m68k-netbsd
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple le32-nacl
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple le64
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple ppc
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple ppc-freebsd
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple ppc-netbsd
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index b3bb354b38ff5..cb2be3bbd29f7 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -88,8 +88,6 @@ class Triple {
xtensa, // Tensilica: Xtensa
nvptx, // NVPTX: 32-bit
nvptx64, // NVPTX: 64-bit
- le32, // le32: generic little-endian 32-bit CPU (PNaCl)
- le64, // le64: generic little-endian 64-bit CPU (PNaCl)
amdil, // AMDIL
amdil64, // AMDIL with 64-bit pointers
hsail, // AMD HSAIL
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 4fc1ff5aaa051..a54a02ac61d68 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -44,8 +44,6 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case hsail: return "hsail";
case kalimba: return "kalimba";
case lanai: return "lanai";
- case le32: return "le32";
- case le64: return "le64";
case loongarch32: return "loongarch32";
case loongarch64: return "loongarch64";
case m68k: return "m68k";
@@ -199,9 +197,6 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case nvptx: return "nvvm";
case nvptx64: return "nvvm";
- case le32: return "le32";
- case le64: return "le64";
-
case amdil:
case amdil64: return "amdil";
@@ -432,8 +427,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("xcore", xcore)
.Case("nvptx", nvptx)
.Case("nvptx64", nvptx64)
- .Case("le32", le32)
- .Case("le64", le64)
.Case("amdil", amdil)
.Case("amdil64", amdil64)
.Case("hsail", hsail)
@@ -574,8 +567,6 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("xcore", Triple::xcore)
.Case("nvptx", Triple::nvptx)
.Case("nvptx64", Triple::nvptx64)
- .Case("le32", Triple::le32)
- .Case("le64", Triple::le64)
.Case("amdil", Triple::amdil)
.Case("amdil64", Triple::amdil64)
.Case("hsail", Triple::hsail)
@@ -905,8 +896,6 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::hsail:
case Triple::kalimba:
case Triple::lanai:
- case Triple::le32:
- case Triple::le64:
case Triple::loongarch32:
case Triple::loongarch64:
case Triple::m68k:
@@ -1603,7 +1592,6 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::hsail:
case llvm::Triple::kalimba:
case llvm::Triple::lanai:
- case llvm::Triple::le32:
case llvm::Triple::loongarch32:
case llvm::Triple::m68k:
case llvm::Triple::mips:
@@ -1636,7 +1624,6 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::bpfeb:
case llvm::Triple::bpfel:
case llvm::Triple::hsail64:
- case llvm::Triple::le64:
case llvm::Triple::loongarch64:
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
@@ -1695,7 +1682,6 @@ Triple Triple::get32BitArchVariant() const {
case Triple::hsail:
case Triple::kalimba:
case Triple::lanai:
- case Triple::le32:
case Triple::loongarch32:
case Triple::m68k:
case Triple::mips:
@@ -1726,7 +1712,6 @@ Triple Triple::get32BitArchVariant() const {
case Triple::aarch64_be: T.setArch(Triple::armeb); break;
case Triple::amdil64: T.setArch(Triple::amdil); break;
case Triple::hsail64: T.setArch(Triple::hsail); break;
- case Triple::le64: T.setArch(Triple::le32); break;
case Triple::loongarch64: T.setArch(Triple::loongarch32); break;
case Triple::mips64:
T.setArch(Triple::mips, getSubArch());
@@ -1781,7 +1766,6 @@ Triple Triple::get64BitArchVariant() const {
case Triple::bpfeb:
case Triple::bpfel:
case Triple::hsail64:
- case Triple::le64:
case Triple::loongarch64:
case Triple::mips64:
case Triple::mips64el:
@@ -1805,7 +1789,6 @@ Triple Triple::get64BitArchVariant() const {
case Triple::arm: T.setArch(Triple::aarch64); break;
case Triple::armeb: T.setArch(Triple::aarch64_be); break;
case Triple::hsail: T.setArch(Triple::hsail64); break;
- case Triple::le32: T.setArch(Triple::le64); break;
case Triple::loongarch32: T.setArch(Triple::loongarch64); break;
case Triple::mips:
T.setArch(Triple::mips64, getSubArch());
@@ -1848,8 +1831,6 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::hsail64:
case Triple::hsail:
case Triple::kalimba:
- case Triple::le32:
- case Triple::le64:
case Triple::loongarch32:
case Triple::loongarch64:
case Triple::msp430:
@@ -1953,8 +1934,6 @@ bool Triple::isLittleEndian() const {
case Triple::hsail64:
case Triple::hsail:
case Triple::kalimba:
- case Triple::le32:
- case Triple::le64:
case Triple::loongarch32:
case Triple::loongarch64:
case Triple::mips64el:
diff --git a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
index 576ab1db54988..d2cf5243627a0 100644
--- a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
@@ -108,7 +108,6 @@ static_library("Basic") {
"Targets/DirectX.cpp",
"Targets/Hexagon.cpp",
"Targets/Lanai.cpp",
- "Targets/Le64.cpp",
"Targets/LoongArch.cpp",
"Targets/M68k.cpp",
"Targets/MSP430.cpp",
|
You can test this locally with the following command:git-clang-format --diff 1860fd049e35055fccac14e439227fae803976b8 7570ec37a8d4abc9ec5a258edd0ba35207710a3a --extensions cpp,c,h -- clang/lib/Basic/Targets.cpp clang/lib/Basic/Targets/OSTargets.h clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/ItaniumCXXABI.cpp clang/lib/Driver/ToolChains/Clang.cpp clang/test/CodeGen/bitfield-access-pad.c clang/test/CodeGen/bitfield-access-unit.c clang/test/CodeGenCXX/bitfield-access-empty.cpp clang/test/CodeGenCXX/bitfield-access-tail.cpp clang/test/Preprocessor/predefined-macros-no-warnings.c llvm/include/llvm/TargetParser/Triple.h llvm/lib/TargetParser/Triple.cppView the diff from clang-format here.diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index cb2be3bbd2..b15d320473 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -46,62 +46,62 @@ public:
enum ArchType {
UnknownArch,
- arm, // ARM (little endian): arm, armv.*, xscale
- armeb, // ARM (big endian): armeb
- aarch64, // AArch64 (little endian): aarch64
- aarch64_be, // AArch64 (big endian): aarch64_be
- aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
- arc, // ARC: Synopsys ARC
- avr, // AVR: Atmel AVR microcontroller
- bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
- bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
- csky, // CSKY: csky
- dxil, // DXIL 32-bit DirectX bytecode
- hexagon, // Hexagon: hexagon
- loongarch32, // LoongArch (32-bit): loongarch32
- loongarch64, // LoongArch (64-bit): loongarch64
- m68k, // M68k: Motorola 680x0 family
- mips, // MIPS: mips, mipsallegrex, mipsr6
- mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
- mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
- mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
- msp430, // MSP430: msp430
- ppc, // PPC: powerpc
- ppcle, // PPCLE: powerpc (little endian)
- ppc64, // PPC64: powerpc64, ppu
- ppc64le, // PPC64LE: powerpc64le
- r600, // R600: AMD GPUs HD2XXX - HD6XXX
- amdgcn, // AMDGCN: AMD GCN GPUs
- riscv32, // RISC-V (32-bit): riscv32
- riscv64, // RISC-V (64-bit): riscv64
- sparc, // Sparc: sparc
- sparcv9, // Sparcv9: Sparcv9
- sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
- systemz, // SystemZ: s390x
- tce, // TCE (http://tce.cs.tut.fi/): tce
- tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
- thumb, // Thumb (little endian): thumb, thumbv.*
- thumbeb, // Thumb (big endian): thumbeb
- x86, // X86: i[3-9]86
- x86_64, // X86-64: amd64, x86_64
- xcore, // XCore: xcore
- xtensa, // Tensilica: Xtensa
- nvptx, // NVPTX: 32-bit
- nvptx64, // NVPTX: 64-bit
- amdil, // AMDIL
- amdil64, // AMDIL with 64-bit pointers
- hsail, // AMD HSAIL
- hsail64, // AMD HSAIL with 64-bit pointers
- spir, // SPIR: standard portable IR for OpenCL 32-bit version
- spir64, // SPIR: standard portable IR for OpenCL 64-bit version
- spirv, // SPIR-V with logical memory layout.
- spirv32, // SPIR-V with 32-bit pointers
- spirv64, // SPIR-V with 64-bit pointers
- kalimba, // Kalimba: generic kalimba
- shave, // SHAVE: Movidius vector VLIW processors
- lanai, // Lanai: Lanai 32-bit
- wasm32, // WebAssembly with 32-bit pointers
- wasm64, // WebAssembly with 64-bit pointers
+ arm, // ARM (little endian): arm, armv.*, xscale
+ armeb, // ARM (big endian): armeb
+ aarch64, // AArch64 (little endian): aarch64
+ aarch64_be, // AArch64 (big endian): aarch64_be
+ aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
+ arc, // ARC: Synopsys ARC
+ avr, // AVR: Atmel AVR microcontroller
+ bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
+ bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
+ csky, // CSKY: csky
+ dxil, // DXIL 32-bit DirectX bytecode
+ hexagon, // Hexagon: hexagon
+ loongarch32, // LoongArch (32-bit): loongarch32
+ loongarch64, // LoongArch (64-bit): loongarch64
+ m68k, // M68k: Motorola 680x0 family
+ mips, // MIPS: mips, mipsallegrex, mipsr6
+ mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
+ mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
+ mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
+ msp430, // MSP430: msp430
+ ppc, // PPC: powerpc
+ ppcle, // PPCLE: powerpc (little endian)
+ ppc64, // PPC64: powerpc64, ppu
+ ppc64le, // PPC64LE: powerpc64le
+ r600, // R600: AMD GPUs HD2XXX - HD6XXX
+ amdgcn, // AMDGCN: AMD GCN GPUs
+ riscv32, // RISC-V (32-bit): riscv32
+ riscv64, // RISC-V (64-bit): riscv64
+ sparc, // Sparc: sparc
+ sparcv9, // Sparcv9: Sparcv9
+ sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+ systemz, // SystemZ: s390x
+ tce, // TCE (http://tce.cs.tut.fi/): tce
+ tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
+ thumb, // Thumb (little endian): thumb, thumbv.*
+ thumbeb, // Thumb (big endian): thumbeb
+ x86, // X86: i[3-9]86
+ x86_64, // X86-64: amd64, x86_64
+ xcore, // XCore: xcore
+ xtensa, // Tensilica: Xtensa
+ nvptx, // NVPTX: 32-bit
+ nvptx64, // NVPTX: 64-bit
+ amdil, // AMDIL
+ amdil64, // AMDIL with 64-bit pointers
+ hsail, // AMD HSAIL
+ hsail64, // AMD HSAIL with 64-bit pointers
+ spir, // SPIR: standard portable IR for OpenCL 32-bit version
+ spir64, // SPIR: standard portable IR for OpenCL 64-bit version
+ spirv, // SPIR-V with logical memory layout.
+ spirv32, // SPIR-V with 32-bit pointers
+ spirv64, // SPIR-V with 64-bit pointers
+ kalimba, // Kalimba: generic kalimba
+ shave, // SHAVE: Movidius vector VLIW processors
+ lanai, // Lanai: Lanai 32-bit
+ wasm32, // WebAssembly with 32-bit pointers
+ wasm64, // WebAssembly with 64-bit pointers
renderscript32, // 32-bit RenderScript
renderscript64, // 64-bit RenderScript
ve, // NEC SX-Aurora Vector Engine
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index a54a02ac61..4b21f9135a 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -43,7 +43,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case hsail64: return "hsail64";
case hsail: return "hsail";
case kalimba: return "kalimba";
- case lanai: return "lanai";
+ case lanai:
+ return "lanai";
case loongarch32: return "loongarch32";
case loongarch64: return "loongarch64";
case m68k: return "m68k";
@@ -385,71 +386,71 @@ static Triple::ArchType parseBPFArch(StringRef ArchName) {
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
Triple::ArchType BPFArch(parseBPFArch(Name));
return StringSwitch<Triple::ArchType>(Name)
- .Case("aarch64", aarch64)
- .Case("aarch64_be", aarch64_be)
- .Case("aarch64_32", aarch64_32)
- .Case("arc", arc)
- .Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
- .Case("arm64_32", aarch64_32)
- .Case("arm", arm)
- .Case("armeb", armeb)
- .Case("avr", avr)
- .StartsWith("bpf", BPFArch)
- .Case("m68k", m68k)
- .Case("mips", mips)
- .Case("mipsel", mipsel)
- .Case("mips64", mips64)
- .Case("mips64el", mips64el)
- .Case("msp430", msp430)
- .Case("ppc64", ppc64)
- .Case("ppc32", ppc)
- .Case("ppc", ppc)
- .Case("ppc32le", ppcle)
- .Case("ppcle", ppcle)
- .Case("ppc64le", ppc64le)
- .Case("r600", r600)
- .Case("amdgcn", amdgcn)
- .Case("riscv32", riscv32)
- .Case("riscv64", riscv64)
- .Case("hexagon", hexagon)
- .Case("sparc", sparc)
- .Case("sparcel", sparcel)
- .Case("sparcv9", sparcv9)
- .Case("s390x", systemz)
- .Case("systemz", systemz)
- .Case("tce", tce)
- .Case("tcele", tcele)
- .Case("thumb", thumb)
- .Case("thumbeb", thumbeb)
- .Case("x86", x86)
- .Case("i386", x86)
- .Case("x86-64", x86_64)
- .Case("xcore", xcore)
- .Case("nvptx", nvptx)
- .Case("nvptx64", nvptx64)
- .Case("amdil", amdil)
- .Case("amdil64", amdil64)
- .Case("hsail", hsail)
- .Case("hsail64", hsail64)
- .Case("spir", spir)
- .Case("spir64", spir64)
- .Case("spirv", spirv)
- .Case("spirv32", spirv32)
- .Case("spirv64", spirv64)
- .Case("kalimba", kalimba)
- .Case("lanai", lanai)
- .Case("shave", shave)
- .Case("wasm32", wasm32)
- .Case("wasm64", wasm64)
- .Case("renderscript32", renderscript32)
- .Case("renderscript64", renderscript64)
- .Case("ve", ve)
- .Case("csky", csky)
- .Case("loongarch32", loongarch32)
- .Case("loongarch64", loongarch64)
- .Case("dxil", dxil)
- .Case("xtensa", xtensa)
- .Default(UnknownArch);
+ .Case("aarch64", aarch64)
+ .Case("aarch64_be", aarch64_be)
+ .Case("aarch64_32", aarch64_32)
+ .Case("arc", arc)
+ .Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
+ .Case("arm64_32", aarch64_32)
+ .Case("arm", arm)
+ .Case("armeb", armeb)
+ .Case("avr", avr)
+ .StartsWith("bpf", BPFArch)
+ .Case("m68k", m68k)
+ .Case("mips", mips)
+ .Case("mipsel", mipsel)
+ .Case("mips64", mips64)
+ .Case("mips64el", mips64el)
+ .Case("msp430", msp430)
+ .Case("ppc64", ppc64)
+ .Case("ppc32", ppc)
+ .Case("ppc", ppc)
+ .Case("ppc32le", ppcle)
+ .Case("ppcle", ppcle)
+ .Case("ppc64le", ppc64le)
+ .Case("r600", r600)
+ .Case("amdgcn", amdgcn)
+ .Case("riscv32", riscv32)
+ .Case("riscv64", riscv64)
+ .Case("hexagon", hexagon)
+ .Case("sparc", sparc)
+ .Case("sparcel", sparcel)
+ .Case("sparcv9", sparcv9)
+ .Case("s390x", systemz)
+ .Case("systemz", systemz)
+ .Case("tce", tce)
+ .Case("tcele", tcele)
+ .Case("thumb", thumb)
+ .Case("thumbeb", thumbeb)
+ .Case("x86", x86)
+ .Case("i386", x86)
+ .Case("x86-64", x86_64)
+ .Case("xcore", xcore)
+ .Case("nvptx", nvptx)
+ .Case("nvptx64", nvptx64)
+ .Case("amdil", amdil)
+ .Case("amdil64", amdil64)
+ .Case("hsail", hsail)
+ .Case("hsail64", hsail64)
+ .Case("spir", spir)
+ .Case("spir64", spir64)
+ .Case("spirv", spirv)
+ .Case("spirv32", spirv32)
+ .Case("spirv64", spirv64)
+ .Case("kalimba", kalimba)
+ .Case("lanai", lanai)
+ .Case("shave", shave)
+ .Case("wasm32", wasm32)
+ .Case("wasm64", wasm64)
+ .Case("renderscript32", renderscript32)
+ .Case("renderscript64", renderscript64)
+ .Case("ve", ve)
+ .Case("csky", csky)
+ .Case("loongarch32", loongarch32)
+ .Case("loongarch64", loongarch64)
+ .Case("dxil", dxil)
+ .Case("xtensa", xtensa)
+ .Default(UnknownArch);
}
static Triple::ArchType parseARMArch(StringRef ArchName) {
@@ -518,84 +519,83 @@ static Triple::ArchType parseARMArch(StringRef ArchName) {
}
static Triple::ArchType parseArch(StringRef ArchName) {
- auto AT =
- StringSwitch<Triple::ArchType>(ArchName)
- .Cases("i386", "i486", "i586", "i686", Triple::x86)
- // FIXME: Do we need to support these?
- .Cases("i786", "i886", "i986", Triple::x86)
- .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
- .Cases("powerpc", "powerpcspe", "ppc", "ppc32", Triple::ppc)
- .Cases("powerpcle", "ppcle", "ppc32le", Triple::ppcle)
- .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
- .Cases("powerpc64le", "ppc64le", Triple::ppc64le)
- .Case("xscale", Triple::arm)
- .Case("xscaleeb", Triple::armeb)
- .Case("aarch64", Triple::aarch64)
- .Case("aarch64_be", Triple::aarch64_be)
- .Case("aarch64_32", Triple::aarch64_32)
- .Case("arc", Triple::arc)
- .Case("arm64", Triple::aarch64)
- .Case("arm64_32", Triple::aarch64_32)
- .Case("arm64e", Triple::aarch64)
- .Case("arm64ec", Triple::aarch64)
- .Case("arm", Triple::arm)
- .Case("armeb", Triple::armeb)
- .Case("thumb", Triple::thumb)
- .Case("thumbeb", Triple::thumbeb)
- .Case("avr", Triple::avr)
- .Case("m68k", Triple::m68k)
- .Case("msp430", Triple::msp430)
- .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6", "mipsr6",
- Triple::mips)
- .Cases("mipsel", "mipsallegrexel", "mipsisa32r6el", "mipsr6el",
- Triple::mipsel)
- .Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6", "mips64r6",
- "mipsn32r6", Triple::mips64)
- .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
- "mipsn32r6el", Triple::mips64el)
- .Case("r600", Triple::r600)
- .Case("amdgcn", Triple::amdgcn)
- .Case("riscv32", Triple::riscv32)
- .Case("riscv64", Triple::riscv64)
- .Case("hexagon", Triple::hexagon)
- .Cases("s390x", "systemz", Triple::systemz)
- .Case("sparc", Triple::sparc)
- .Case("sparcel", Triple::sparcel)
- .Cases("sparcv9", "sparc64", Triple::sparcv9)
- .Case("tce", Triple::tce)
- .Case("tcele", Triple::tcele)
- .Case("xcore", Triple::xcore)
- .Case("nvptx", Triple::nvptx)
- .Case("nvptx64", Triple::nvptx64)
- .Case("amdil", Triple::amdil)
- .Case("amdil64", Triple::amdil64)
- .Case("hsail", Triple::hsail)
- .Case("hsail64", Triple::hsail64)
- .Case("spir", Triple::spir)
- .Case("spir64", Triple::spir64)
- .Cases("spirv", "spirv1.5", "spirv1.6", Triple::spirv)
- .Cases("spirv32", "spirv32v1.0", "spirv32v1.1", "spirv32v1.2",
- "spirv32v1.3", "spirv32v1.4", "spirv32v1.5",
- "spirv32v1.6", Triple::spirv32)
- .Cases("spirv64", "spirv64v1.0", "spirv64v1.1", "spirv64v1.2",
- "spirv64v1.3", "spirv64v1.4", "spirv64v1.5",
- "spirv64v1.6", Triple::spirv64)
- .StartsWith("kalimba", Triple::kalimba)
- .Case("lanai", Triple::lanai)
- .Case("renderscript32", Triple::renderscript32)
- .Case("renderscript64", Triple::renderscript64)
- .Case("shave", Triple::shave)
- .Case("ve", Triple::ve)
- .Case("wasm32", Triple::wasm32)
- .Case("wasm64", Triple::wasm64)
- .Case("csky", Triple::csky)
- .Case("loongarch32", Triple::loongarch32)
- .Case("loongarch64", Triple::loongarch64)
- .Cases("dxil", "dxilv1.0", "dxilv1.1", "dxilv1.2", "dxilv1.3",
- "dxilv1.4", "dxilv1.5", "dxilv1.6", "dxilv1.7", "dxilv1.8",
- Triple::dxil)
- .Case("xtensa", Triple::xtensa)
- .Default(Triple::UnknownArch);
+ auto AT = StringSwitch<Triple::ArchType>(ArchName)
+ .Cases("i386", "i486", "i586", "i686", Triple::x86)
+ // FIXME: Do we need to support these?
+ .Cases("i786", "i886", "i986", Triple::x86)
+ .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
+ .Cases("powerpc", "powerpcspe", "ppc", "ppc32", Triple::ppc)
+ .Cases("powerpcle", "ppcle", "ppc32le", Triple::ppcle)
+ .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
+ .Cases("powerpc64le", "ppc64le", Triple::ppc64le)
+ .Case("xscale", Triple::arm)
+ .Case("xscaleeb", Triple::armeb)
+ .Case("aarch64", Triple::aarch64)
+ .Case("aarch64_be", Triple::aarch64_be)
+ .Case("aarch64_32", Triple::aarch64_32)
+ .Case("arc", Triple::arc)
+ .Case("arm64", Triple::aarch64)
+ .Case("arm64_32", Triple::aarch64_32)
+ .Case("arm64e", Triple::aarch64)
+ .Case("arm64ec", Triple::aarch64)
+ .Case("arm", Triple::arm)
+ .Case("armeb", Triple::armeb)
+ .Case("thumb", Triple::thumb)
+ .Case("thumbeb", Triple::thumbeb)
+ .Case("avr", Triple::avr)
+ .Case("m68k", Triple::m68k)
+ .Case("msp430", Triple::msp430)
+ .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
+ "mipsr6", Triple::mips)
+ .Cases("mipsel", "mipsallegrexel", "mipsisa32r6el", "mipsr6el",
+ Triple::mipsel)
+ .Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6",
+ "mips64r6", "mipsn32r6", Triple::mips64)
+ .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
+ "mipsn32r6el", Triple::mips64el)
+ .Case("r600", Triple::r600)
+ .Case("amdgcn", Triple::amdgcn)
+ .Case("riscv32", Triple::riscv32)
+ .Case("riscv64", Triple::riscv64)
+ .Case("hexagon", Triple::hexagon)
+ .Cases("s390x", "systemz", Triple::systemz)
+ .Case("sparc", Triple::sparc)
+ .Case("sparcel", Triple::sparcel)
+ .Cases("sparcv9", "sparc64", Triple::sparcv9)
+ .Case("tce", Triple::tce)
+ .Case("tcele", Triple::tcele)
+ .Case("xcore", Triple::xcore)
+ .Case("nvptx", Triple::nvptx)
+ .Case("nvptx64", Triple::nvptx64)
+ .Case("amdil", Triple::amdil)
+ .Case("amdil64", Triple::amdil64)
+ .Case("hsail", Triple::hsail)
+ .Case("hsail64", Triple::hsail64)
+ .Case("spir", Triple::spir)
+ .Case("spir64", Triple::spir64)
+ .Cases("spirv", "spirv1.5", "spirv1.6", Triple::spirv)
+ .Cases("spirv32", "spirv32v1.0", "spirv32v1.1", "spirv32v1.2",
+ "spirv32v1.3", "spirv32v1.4", "spirv32v1.5",
+ "spirv32v1.6", Triple::spirv32)
+ .Cases("spirv64", "spirv64v1.0", "spirv64v1.1", "spirv64v1.2",
+ "spirv64v1.3", "spirv64v1.4", "spirv64v1.5",
+ "spirv64v1.6", Triple::spirv64)
+ .StartsWith("kalimba", Triple::kalimba)
+ .Case("lanai", Triple::lanai)
+ .Case("renderscript32", Triple::renderscript32)
+ .Case("renderscript64", Triple::renderscript64)
+ .Case("shave", Triple::shave)
+ .Case("ve", Triple::ve)
+ .Case("wasm32", Triple::wasm32)
+ .Case("wasm64", Triple::wasm64)
+ .Case("csky", Triple::csky)
+ .Case("loongarch32", Triple::loongarch32)
+ .Case("loongarch64", Triple::loongarch64)
+ .Cases("dxil", "dxilv1.0", "dxilv1.1", "dxilv1.2", "dxilv1.3",
+ "dxilv1.4", "dxilv1.5", "dxilv1.6", "dxilv1.7",
+ "dxilv1.8", Triple::dxil)
+ .Case("xtensa", Triple::xtensa)
+ .Default(Triple::UnknownArch);
// Some architectures require special parsing logic just to compute the
// ArchType result.
@@ -1711,7 +1711,9 @@ Triple Triple::get32BitArchVariant() const {
case Triple::aarch64: T.setArch(Triple::arm); break;
case Triple::aarch64_be: T.setArch(Triple::armeb); break;
case Triple::amdil64: T.setArch(Triple::amdil); break;
- case Triple::hsail64: T.setArch(Triple::hsail); break;
+ case Triple::hsail64:
+ T.setArch(Triple::hsail);
+ break;
case Triple::loongarch64: T.setArch(Triple::loongarch32); break;
case Triple::mips64:
T.setArch(Triple::mips, getSubArch());
@@ -1788,7 +1790,9 @@ Triple Triple::get64BitArchVariant() const {
case Triple::amdil: T.setArch(Triple::amdil64); break;
case Triple::arm: T.setArch(Triple::aarch64); break;
case Triple::armeb: T.setArch(Triple::aarch64_be); break;
- case Triple::hsail: T.setArch(Triple::hsail64); break;
+ case Triple::hsail:
+ T.setArch(Triple::hsail64);
+ break;
case Triple::loongarch32: T.setArch(Triple::loongarch64); break;
case Triple::mips:
T.setArch(Triple::mips64, getSubArch());
|
dschuff
reviewed
Jul 11, 2024
|
Precommit CI failure on Windows appears to be unrelated: |
MaskRay
approved these changes
Jul 11, 2024
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/2149 Here is the relevant piece of the build log for the reference: |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/46/builds/1534 Here is the relevant piece of the build log for the reference: |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/65/builds/1309 Here is the relevant piece of the build log for the reference: |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/154/builds/1300 Here is the relevant piece of the build log for the reference: |
aaryanshukla
pushed a commit
to aaryanshukla/llvm-project
that referenced
this pull request
Jul 14, 2024
|
Unfortunately, this utterly breaks Halide, which was in fact relying on both of these targets. |
I understand that you want these gone, but the fact of the matter is that Halide isn't ready for this change, and so the next integrate of LLVM into google3 will break the world. We urgently need these features (or something like them). |
|
It looks like the removal missed a few bits: PNaClABIBuiltinVaList and clang/lib/CodeGen/Targets/PNaCl.cpp weren't removed.
We can temporarily revert this, but we aren't going to leave the orphaned remains of PNaCl in-tree forever. If you need a "halide" target long-term, please write up a proposal on Discourse describing exactly what bits you need, why you need them, relevant test coverage in-tree and out-of-tree, and a proposed code owner for those bits. |
|
It seems that Halide (halide/Halide#5934), an important user, still needs generic 32-bit 64-bit Clang targets. @AaronBallman Are you comfortable with bring back le32/le64 temporarily? The le32/le64 targets, while they lived in Clang and could be brought back again, their testing in tree was really thin and any reliance on particular behaviors could be fragile... |
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Our actual need is for a stable and user-friendly way to write fragments of mostly-target-agnostic llvm IR. We concat these with other fragments and give it an actual target triple later. This lets us assemble a target-specific Halide runtime dynamically by mixing and matching some number of these fragments. Compiling these fragments for all possible target triples we support instead of a generic one would multiply our code size and compile time by the (large) number of possible target triples we can emit. Not using fragments at all and compiling a runtime in a more conventional way would be a combinatorial amount of code, because there are a lot of combinations. Writing generic .ll directly is possible, and we do a little of that for very low-level things, but writing in C++ and compiling via clang to le64/32 is more stable and much more pleasant due to the abstractions that C++ provides. We just have to be careful to not do things like have structs that would have different layouts on different platforms. If there's a better way to do all this, let us know. Does no other project have a need for "generic" llvm IR without any target-specific annotations on it yet? |
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There is no such thing as "generic" LLVM IR, in general: so many target-specific aspects of C have to be directly encoded into the IR, so there's no way to actually make it generic. In this respect, the "le32/le64" targets aren't really any more generic than any other target; they encode their own specific assumptions, and they're not ABI-compatible with code generated for any other target. The closest you can get to being "generic" is picking a target that's intended to be compiled to other targets, like SPIRV/wasm/etc. So the question is, why specifically use the PNaCl targets, instead of just using the existing Arm or wasm targets? |
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We were advised to use the pnacl targets at the time the code was written. We're trying wasm now. The IR can be generic if you use a subset of C that excludes all the things that vary across the targets you care about. For cases we really can't avoid it (e.g. win32 calling convention stuff for direct3d), we compile that one fragment with a few different target triples. |
This looked promising in our GitHub tests, but for reasons that aren't clear (yet), ~everything compiled this way inside google3 resulted in linker errors (missing symbols). |
You can sort of make this work, I guess. We don't document any such subset, though, and some of the issues aren't obvious at first glance. |
I was under the impression those bits were still needed for Chromium. CC @dschuff
I'm comfortable with a second temporary revert if it's necessary so long as there's a time limit attached to it. The first attempted removal was over three years ago, so if Halide needs this target beyond Clang 20 (roughly six months from now), I think that they need to come to the community with a new proposed timeline for removal or a proposal for official target support of some kind (which requires additional maintenance beyond what the status quo is -- this target has very little in the way of testing or documentation). |
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After some initial experiments, it looks unlikely that a quick fix is possible on our side. May I suggest a revert with a (say) 30-day expiration date? That should give us enough time to come up with a fix on our side (which will actually be a drop-other-work-and-fix-it approach this time). |
Thank you for the investigations -- thirty days seems extremely reasonable to me. If you run into issues while fixing it on your end and need more than thirty days, that's also fine (we can figure out how much longer to wait at that point). I'll get the revert done shortly. |
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This reverts commit 2369a54.
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Reverts #98497 We're reverting this for approx 30 days so that the Halide project has time to transition off the target.
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d3f8105 restores the targets, thank you all for the discussion! |
Oh, clang/lib/CodeGen/Targets/PNaCl.cpp is still live for mipsel-nacl target triple. Which we also have zero tests for, but I guess that's a separate issue. |
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Reverts llvm#98497 We're reverting this for approx 30 days so that the Halide project has time to transition off the target.
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Summary: Reverts #98497 We're reverting this for approx 30 days so that the Halide project has time to transition off the target. Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251543
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Note that Halide has removed its dependency on the le32/le64 targets as of halide/Halide#8344. |
Thank you for letting us know! Does anyone know of any reasons we should not revert the revert (so le32/le64 is removed in Clang 20)? |
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This reverts commit d3f8105. Halide no longer relies on this target: llvm#98497 (comment)
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This reverts commit d3f8105. Halide no longer relies on this target: #98497 (comment)
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…1983) This reverts commit d3f8105. Halide no longer relies on this target: llvm#98497 (comment)
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…1983) This reverts commit d3f8105. Halide no longer relies on this target: llvm#98497 (comment)
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This is a revert of ef5e7f9 which was a temporary partial revert of 77ac823. The le32 and le64 targets are no longer necessary to retain, so this removes them entirely.