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[BOLT][NFC] Infailable fns return void #92018

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Jun 7, 2024
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[BOLT][NFC] Infailable fns return void #92018

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10 changes: 2 additions & 8 deletions bolt/include/bolt/Core/MCPlusBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1706,12 +1706,9 @@ class MCPlusBuilder {
}

/// Reverses the branch condition in Inst and update its taken target to TBB.
///
/// Returns true on success.
virtual bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
virtual void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
return false;
}

virtual bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB,
Expand Down Expand Up @@ -1751,12 +1748,9 @@ class MCPlusBuilder {
}

/// Sets the taken target of the branch instruction to Target.
///
/// Returns true on success.
virtual bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
virtual void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
return false;
}

/// Extract a symbol and an addend out of the fixup value expression.
Expand Down
7 changes: 2 additions & 5 deletions bolt/lib/Passes/VeneerElimination.cpp
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Expand Up @@ -77,11 +77,8 @@ Error VeneerElimination::runOnFunctions(BinaryContext &BC) {
continue;

VeneerCallers++;
if (!BC.MIB->replaceBranchTarget(
Instr, VeneerDestinations[TargetSymbol], BC.Ctx.get())) {
return createFatalBOLTError(
"BOLT-ERROR: updating veneer call destination failed\n");
}
BC.MIB->replaceBranchTarget(Instr, VeneerDestinations[TargetSymbol],
BC.Ctx.get());
}
}
}
Expand Down
7 changes: 3 additions & 4 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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Expand Up @@ -616,7 +616,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return getTargetAddend(Op.getExpr());
}

bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
Expand All @@ -638,7 +638,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {

*OI = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}

/// Matches indirect branch patterns in AArch64 related to a jump table (JT),
Expand Down Expand Up @@ -969,7 +968,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}

bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
if (isTB(Inst) || isCB(Inst)) {
Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode()));
Expand All @@ -984,7 +983,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
LLVM_DEBUG(Inst.dump());
llvm_unreachable("Unrecognized branch instruction");
}
return replaceBranchTarget(Inst, TBB, Ctx);
replaceBranchTarget(Inst, TBB, Ctx);
}

int getPCRelEncodingSize(const MCInst &Inst) const override {
Expand Down
7 changes: 3 additions & 4 deletions bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
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Expand Up @@ -151,14 +151,14 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
}
}

bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
auto Opcode = getInvertedBranchOpcode(Inst.getOpcode());
Inst.setOpcode(Opcode);
return replaceBranchTarget(Inst, TBB, Ctx);
replaceBranchTarget(Inst, TBB, Ctx);
}

bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
Expand All @@ -170,7 +170,6 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {

Inst.getOperand(SymOpIndex) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}

IndirectBranchType analyzeIndirectBranch(
Expand Down
6 changes: 2 additions & 4 deletions bolt/lib/Target/X86/X86MCPlusBuilder.cpp
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Expand Up @@ -2782,14 +2782,13 @@ class X86MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createImm(CC));
}

bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
unsigned InvCC = getInvertedCondCode(getCondCode(Inst));
assert(InvCC != X86::COND_INVALID && "invalid branch instruction");
Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC);
Inst.getOperand(0) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}

bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx,
Expand Down Expand Up @@ -2832,13 +2831,12 @@ class X86MCPlusBuilder : public MCPlusBuilder {
}
}

bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction");
Inst.getOperand(0) = MCOperand::createExpr(
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
return true;
}

MCPhysReg getX86R11() const override { return X86::R11; }
Expand Down
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