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Revert "[Hexagon] Optimize post-increment load and stores in loops. (… #83151

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merged 1 commit into from
Feb 27, 2024
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Revert "[Hexagon] Optimize post-increment load and stores in loops. (… #83151

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1 change: 0 additions & 1 deletion llvm/lib/Target/Hexagon/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@ add_llvm_target(HexagonCodeGen
HexagonOptAddrMode.cpp
HexagonOptimizeSZextends.cpp
HexagonPeephole.cpp
HexagonPostIncOpt.cpp
HexagonRDFOpt.cpp
HexagonRegisterInfo.cpp
HexagonSelectionDAGInfo.cpp
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56 changes: 0 additions & 56 deletions llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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Expand Up @@ -1655,13 +1655,6 @@ bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
return getAddrMode(MI) == HexagonII::PostInc;
}

bool HexagonInstrInfo::isPostIncWithImmOffset(const MachineInstr &MI) const {
unsigned BasePos, OffsetPos;
if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
return false;
return isPostIncrement(MI) && MI.getOperand(OffsetPos).isImm();
}

// Returns true if an instruction is predicated irrespective of the predicate
// sense. For example, all of the following will return true.
// if (p0) R1 = add(R2, R3)
Expand Down Expand Up @@ -2443,55 +2436,6 @@ bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
Opcode == Hexagon::J2_loop1rext;
}

bool HexagonInstrInfo::isCircBufferInstr(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return false;
case Hexagon::L2_loadalignb_pci:
case Hexagon::L2_loadalignb_pcr:
case Hexagon::L2_loadalignh_pci:
case Hexagon::L2_loadalignh_pcr:
case Hexagon::L2_loadbsw2_pci:
case Hexagon::L2_loadbsw2_pcr:
case Hexagon::L2_loadbsw4_pci:
case Hexagon::L2_loadbsw4_pcr:
case Hexagon::L2_loadbzw2_pci:
case Hexagon::L2_loadbzw2_pcr:
case Hexagon::L2_loadbzw4_pci:
case Hexagon::L2_loadbzw4_pcr:
case Hexagon::L2_loadrb_pci:
case Hexagon::L2_loadrb_pcr:
case Hexagon::L2_loadrd_pci:
case Hexagon::L2_loadrd_pcr:
case Hexagon::L2_loadrh_pci:
case Hexagon::L2_loadrh_pcr:
case Hexagon::L2_loadri_pci:
case Hexagon::L2_loadri_pcr:
case Hexagon::L2_loadrub_pci:
case Hexagon::L2_loadrub_pcr:
case Hexagon::L2_loadruh_pci:
case Hexagon::L2_loadruh_pcr:
case Hexagon::S2_storerbnew_pci:
case Hexagon::S2_storerbnew_pcr:
case Hexagon::S2_storerb_pci:
case Hexagon::S2_storerb_pcr:
case Hexagon::S2_storerd_pci:
case Hexagon::S2_storerd_pcr:
case Hexagon::S2_storerf_pci:
case Hexagon::S2_storerf_pcr:
case Hexagon::S2_storerhnew_pci:
case Hexagon::S2_storerhnew_pcr:
case Hexagon::S2_storerh_pci:
case Hexagon::S2_storerh_pcr:
case Hexagon::S2_storerinew_pci:
case Hexagon::S2_storerinew_pcr:
case Hexagon::S2_storeri_pci:
case Hexagon::S2_storeri_pcr:
return true;
}
return false;
}

bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default: return false;
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2 changes: 0 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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Expand Up @@ -434,8 +434,6 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
bool isPostIncWithImmOffset(const MachineInstr &MI) const;
bool isCircBufferInstr(const MachineInstr &MI) const;

unsigned getAddrMode(const MachineInstr &MI) const;
MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
Expand Down
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