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[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. #71483

Merged
merged 4 commits into from
Nov 7, 2023
Merged

[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. #71483

merged 4 commits into from
Nov 7, 2023

Commits on Nov 7, 2023

  1. [RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. 

    This transformation is illegal for PseduoVIOTA_M. The value of `viota.m vd, vs2`
is the prefix sum of vd2 and adding mask for it may cause wrong prefix sum.

Take an example, the result of following expression is `{5, 5, 5, 3}`,
```
; v4 = {1, 1, 1, 1}
viota.m v1, v4
; v0 = {0, 0, 0, 1}, v1 = {0, 1, 2, 3}, v8 = {5, 5, 5, 5}
vmerge.vvm v8, v8, v1, v0.t
; v8 = {5, 5, 5, 3}
```
but if we merge them to `viota.m v8, v4, v0.t`, then the result of is
`{5, 5, 5, 0}`

We still does the transformation when mask of vmerge.vvm is a true mask.
    Yeting Kuo committed Nov 7, 2023
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  2. Use getRVVMCOpcode to avoid list all pseduo instruction.

    Yeting Kuo committed Nov 7, 2023
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  3. Add isAccumulated bit for RISCVMaskedPseudoInfo.

    Yeting Kuo committed Nov 7, 2023
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  4. Rename IsAccumulatedOp to MaskAffectsResult.

    Yeting Kuo committed Nov 7, 2023
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