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[GlobalISel] Fall back for bf16 conversions. #71470

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Nov 7, 2023
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[GlobalISel] Fall back for bf16 conversions. #71470

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3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1484,6 +1484,9 @@ bool IRTranslator::translateBitCast(const User &U,

bool IRTranslator::translateCast(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
if (U.getType()->getScalarType()->isBFloatTy() ||
U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
return false;
Register Op = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);
MIRBuilder.buildInstr(Opcode, {Res}, {Op});
Expand Down
386 changes: 120 additions & 266 deletions llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
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219 changes: 72 additions & 147 deletions llvm/test/CodeGen/AMDGPU/llvm.exp.ll
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
Expand Down Expand Up @@ -5763,152 +5763,77 @@ define float @v_exp_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}

define float @v_exp_f32_from_fpext_bf16(bfloat %src) {
; VI-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v2
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, v3
; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; VI-LABEL: v_exp_f32_from_fpext_bf16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-NEXT: v_sub_f32_e32 v4, v0, v1
; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
; VI-NEXT: v_rndne_f32_e32 v3, v2
; VI-NEXT: v_add_f32_e32 v4, v4, v5
; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-NEXT: v_sub_f32_e32 v2, v2, v3
; VI-NEXT: v_add_f32_e32 v1, v1, v4
; VI-NEXT: v_add_f32_e32 v1, v2, v1
; VI-NEXT: v_exp_f32_e32 v1, v1
; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-NEXT: s_mov_b32 s4, 0x42b17218
; VI-NEXT: v_ldexp_f32 v1, v1, v2
; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX900-LABEL: v_exp_f32_from_fpext_bf16:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-NEXT: v_exp_f32_e32 v1, v1
; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, v3
; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4
; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; SI-LABEL: v_exp_f32_from_fpext_bf16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-NEXT: v_rndne_f32_e32 v2, v1
; SI-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-NEXT: v_add_f32_e32 v1, v3, v1
; SI-NEXT: v_exp_f32_e32 v1, v1
; SI-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-NEXT: s_mov_b32 s4, 0x42b17218
; SI-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp_f32_from_fpext_bf16:
; R600: ; %bb.0:
Expand Down
39 changes: 16 additions & 23 deletions llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
Expand Down Expand Up @@ -1992,26 +1992,19 @@ define float @v_exp2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}

define float @v_exp2_f32_from_fpext_bf16(bfloat %src) {
; GCN-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GCN-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: v_exp2_f32_from_fpext_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, 0xc2fc0000
; GCN-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GCN-NEXT: v_mov_b32_e32 v2, 0x42800000
; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GCN-NEXT: v_add_f32_e32 v0, v0, v2
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GCN-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp2_f32_from_fpext_bf16:
; R600: ; %bb.0:
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