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[AMDGPU] Fix cost of fast unsafe f32 fdiv #68988

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Merged
merged 1 commit into from
Oct 15, 2023
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[AMDGPU] Fix cost of fast unsafe f32 fdiv #68988

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9 changes: 9 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -650,6 +650,15 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
return LT.first * Cost * NElts;
}

if (SLT == MVT::f32 && ((CxtI && CxtI->hasApproxFunc()) ||
TLI->getTargetMachine().Options.UnsafeFPMath)) {
// Fast unsafe fdiv lowering:
// f32 rcp
// f32 fmul
int Cost = getQuarterRateInstrCost(CostKind) + getFullRateInstrCost();
return LT.first * Cost * NElts;
}

if (SLT == MVT::f32 || SLT == MVT::f16) {
// 4 more v_cvt_* insts without f16 insts support
int Cost = (SLT == MVT::f16 ? 14 : 10) * getFullRateInstrCost() +
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62 changes: 62 additions & 0 deletions llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
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Expand Up @@ -43,6 +43,37 @@ define amdgpu_kernel void @fdiv_f32_ieee() #0 {
ret void
}

define amdgpu_kernel void @fdiv_f32_afn_ieee() #0 {
; ALL-LABEL: 'fdiv_f32_afn_ieee'
; ALL-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %f32 = fdiv afn float undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f32 = fdiv afn <2 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v3f32 = fdiv afn <3 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f32 = fdiv afn <4 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %v5f32 = fdiv afn <5 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f32 = fdiv afn <8 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %v9f32 = fdiv afn <9 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'fdiv_f32_afn_ieee'
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %f32 = fdiv afn float undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v2f32 = fdiv afn <2 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v3f32 = fdiv afn <3 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4f32 = fdiv afn <4 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v5f32 = fdiv afn <5 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v8f32 = fdiv afn <8 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %v9f32 = fdiv afn <9 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f32 = fdiv afn float undef, undef
%v2f32 = fdiv afn <2 x float> undef, undef
%v3f32 = fdiv afn <3 x float> undef, undef
%v4f32 = fdiv afn <4 x float> undef, undef
%v5f32 = fdiv afn <5 x float> undef, undef
%v8f32 = fdiv afn <8 x float> undef, undef
%v9f32 = fdiv afn <9 x float> undef, undef
ret void
}

define amdgpu_kernel void @fdiv_f32_ftzdaz() #1 {
; ALL-LABEL: 'fdiv_f32_ftzdaz'
; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f32 = fdiv float undef, undef
Expand Down Expand Up @@ -74,6 +105,37 @@ define amdgpu_kernel void @fdiv_f32_ftzdaz() #1 {
ret void
}

define amdgpu_kernel void @fdiv_f32_afn_ftzdaz() #1 {
; ALL-LABEL: 'fdiv_f32_afn_ftzdaz'
; ALL-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %f32 = fdiv afn float undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f32 = fdiv afn <2 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v3f32 = fdiv afn <3 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v4f32 = fdiv afn <4 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %v5f32 = fdiv afn <5 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v8f32 = fdiv afn <8 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %v9f32 = fdiv afn <9 x float> undef, undef
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'fdiv_f32_afn_ftzdaz'
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %f32 = fdiv afn float undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v2f32 = fdiv afn <2 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v3f32 = fdiv afn <3 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v4f32 = fdiv afn <4 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v5f32 = fdiv afn <5 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v8f32 = fdiv afn <8 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %v9f32 = fdiv afn <9 x float> undef, undef
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f32 = fdiv afn float undef, undef
%v2f32 = fdiv afn <2 x float> undef, undef
%v3f32 = fdiv afn <3 x float> undef, undef
%v4f32 = fdiv afn <4 x float> undef, undef
%v5f32 = fdiv afn <5 x float> undef, undef
%v8f32 = fdiv afn <8 x float> undef, undef
%v9f32 = fdiv afn <9 x float> undef, undef
ret void
}

define amdgpu_kernel void @fdiv_f64() #0 {
; CIFASTF64-LABEL: 'fdiv_f64'
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %f64 = fdiv double undef, undef
Expand Down