Commits on Sep 14, 2023

1. [AArch64] Split Ampere1Write_Arith into rr/ri and rs/rx InstRWs. …

   The ampere1 scheduling model uses IsCheapLSL predicates for ADDXri and ADDWrr
   instructions, which only have 3 operands. In attempting to check that the third
   is a shift, the predicate can attempt to access an out of bounds operand,
   hitting an assert. This splits the rr/ri instructions (which can never have
   shifts) from the rs/rx instructions to ensure they both work correctly.
   Ampere1Write_1cyc_1AB was chosen for the rr/ir instructions to match the cheap
   case.
   
   This also sets CompleteModel = 0 for the ampere1 scheduling model, as at
   runtime under debug it will attempt to check that as well as all instructions
   having scheduling info, there is information for each output operand.
   
   DefIdx 1 exceeds machine model writes for
     renamable $w9, renamable $w8 = LDPWi renamable $x8, 0
   (Try with MCSchedModel.CompleteModel set to false)incomplete machine model

   

   davemgreen committed Sep 14, 2023
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