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[Mips] Fix compiler crash when returning fp128 after calling a functi… #117525

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Jan 20, 2025
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[Mips] Fix compiler crash when returning fp128 after calling a functi… #117525

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0e1f468
[Mips] Fix compiler crash when returning fp128 after calling a functi…
yingopq Nov 25, 2024
6c660f1
Merge branch 'main' into Fix_bug_issue_96432
yingopq Dec 26, 2024
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2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/TargetLowering.h
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Expand Up @@ -4781,7 +4781,7 @@ class TargetLowering : public TargetLoweringBase {
virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
MachineFunction &/*MF*/, bool /*isVarArg*/,
const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
LLVMContext &/*Context*/) const
LLVMContext &/*Context*/, const Type *RetTy) const
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A new parameter should not be necessary. Outs should already correspond to the decomposed aggregate type derived from the original IR type

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Because in Mips backend, when process hook function CanLowerReturn, they now use MF function return type to check whether call function return type was origin from fp128.
In fact, when they check whether MF function return type was origin from fp128, they should use MF function return type; when they check whether call function return type was origin from fp128, they should use call function return type.
So, we need a new parameter to specify the right return type.

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We can know each element value type in Outs, but we can not get the call return type from Outs. So I think it is necessary to add a new parameter.

{
// Return true by default to get preexisting behavior.
return true;
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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Expand Up @@ -1001,7 +1001,7 @@ bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);

bool CanLowerReturn = TLI.CanLowerReturn(
CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);

// FIXME: sret demotion isn't supported yet - bail out.
if (!CanLowerReturn)
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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Expand Up @@ -99,7 +99,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
mf.getDataLayout());
CanLowerReturn =
TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext(), Fn->getReturnType());

// If this personality uses funclets, we need to do a bit more work.
DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -11008,7 +11008,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {

bool CanLowerReturn =
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
CLI.IsVarArg, Outs, CLI.RetTy->getContext());
CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);

SDValue DemoteStackSlot;
int DemoteStackIdx = -100;
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -9632,7 +9632,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,

bool AArch64TargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Expand Up @@ -1102,7 +1102,7 @@ class AArch64TargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -3146,7 +3146,8 @@ SDValue SITargetLowering::LowerFormalArguments(
// possible in registers before passing on stack.
bool SITargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
// Replacing returns with sret/stack usage doesn't make sense for shaders.
// FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
// for shaders. Vector types should be explicitly handled by CC.
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.h
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Expand Up @@ -388,7 +388,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARC/ARCISelLowering.cpp
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Expand Up @@ -630,7 +630,8 @@ SDValue ARCTargetLowering::LowerCallArguments(

bool ARCTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCISelLowering.h
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Expand Up @@ -112,7 +112,7 @@ class ARCTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
};
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -3239,7 +3239,7 @@ bool
ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
LLVMContext &Context, const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -965,7 +965,7 @@ class VectorType;
bool CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AVR/AVRISelLowering.cpp
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Expand Up @@ -1670,7 +1670,8 @@ SDValue AVRTargetLowering::LowerCallResult(

bool AVRTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
if (CallConv == CallingConv::AVR_BUILTIN) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/AVRISelLowering.h
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Expand Up @@ -172,7 +172,7 @@ class AVRTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/CSKY/CSKYISelLowering.cpp
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Expand Up @@ -426,7 +426,8 @@ SDValue CSKYTargetLowering::LowerFormalArguments(

bool CSKYTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> CSKYLocs;
CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
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2 changes: 1 addition & 1 deletion llvm/lib/Target/CSKY/CSKYISelLowering.h
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Expand Up @@ -61,7 +61,7 @@ class CSKYTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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Expand Up @@ -182,7 +182,7 @@ bool
HexagonTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
LLVMContext &Context, const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

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2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonISelLowering.h
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Expand Up @@ -249,7 +249,7 @@ class HexagonTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Lanai/LanaiISelLowering.cpp
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Expand Up @@ -527,7 +527,8 @@ SDValue LanaiTargetLowering::LowerCCCArguments(

bool LanaiTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

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2 changes: 1 addition & 1 deletion llvm/lib/Target/Lanai/LanaiISelLowering.h
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Expand Up @@ -93,7 +93,7 @@ class LanaiTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
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3 changes: 2 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Expand Up @@ -5668,7 +5668,8 @@ LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,

bool LoongArchTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

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2 changes: 1 addition & 1 deletion llvm/lib/Target/LoongArch/LoongArchISelLowering.h
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Expand Up @@ -183,7 +183,7 @@ class LoongArchTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/M68k/M68kISelLowering.cpp
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Expand Up @@ -1060,7 +1060,8 @@ SDValue M68kTargetLowering::LowerFormalArguments(

bool M68kTargetLowering::CanLowerReturn(
CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, RetCC_M68k);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/M68k/M68kISelLowering.h
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Expand Up @@ -271,7 +271,7 @@ class M68kTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

/// Lower the result values of a call into the
/// appropriate copies out of appropriate physical registers.
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3 changes: 2 additions & 1 deletion llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
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Expand Up @@ -723,7 +723,8 @@ MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, RetCC_MSP430);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MSP430ISelLowering.h
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Expand Up @@ -171,7 +171,7 @@ namespace llvm {
MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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9 changes: 4 additions & 5 deletions llvm/lib/Target/Mips/MipsCCState.cpp
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Expand Up @@ -95,14 +95,13 @@ void MipsCCState::PreAnalyzeCallResultForF128(

/// Identify lowered values that originated from f128 or float arguments and
/// record this for use by RetCC_MipsN.
void MipsCCState::PreAnalyzeReturnForF128(
const SmallVectorImpl<ISD::OutputArg> &Outs) {
const MachineFunction &MF = getMachineFunction();
void MipsCCState::PreAnalyzeCallReturnForF128(
const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy) {
for (unsigned i = 0; i < Outs.size(); ++i) {
OriginalArgWasF128.push_back(
originalTypeIsF128(MF.getFunction().getReturnType(), nullptr));
originalTypeIsF128(RetTy, nullptr));
OriginalArgWasFloat.push_back(
MF.getFunction().getReturnType()->isFloatingPointTy());
RetTy->isFloatingPointTy());
}
}
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Can we drop PreAnalyzeReturnForF128 now? It should be the same as PreAnalyzeCallReturnForF128 and passing MD.getFunction().getReturnType().

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OK, good idea.

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Can we drop PreAnalyzeReturnForF128 now? It should be the same as PreAnalyzeCallReturnForF128 and passing MD.getFunction().getReturnType().

Applied.

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Ping


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18 changes: 15 additions & 3 deletions llvm/lib/Target/Mips/MipsCCState.h
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Expand Up @@ -49,7 +49,7 @@ class MipsCCState : public CCState {

/// Identify lowered values that originated from f128 arguments and record
/// this for use by RetCC_MipsN.
void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
void PreAnalyzeCallReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy);

/// Identify lowered values that originated from f128 arguments and record
/// this.
Expand Down Expand Up @@ -167,10 +167,11 @@ class MipsCCState : public CCState {

void PreAnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
CCAssignFn Fn) {
const MachineFunction &MF = getMachineFunction();
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
OriginalArgWasFloatVector.clear();
PreAnalyzeReturnForF128(Outs);
PreAnalyzeCallReturnForF128(Outs, MF.getFunction().getReturnType());
PreAnalyzeReturnForVectorFloat(Outs);
}

Expand All @@ -182,7 +183,8 @@ class MipsCCState : public CCState {

bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
CCAssignFn Fn) {
PreAnalyzeReturnForF128(ArgsFlags);
const MachineFunction &MF = getMachineFunction();
PreAnalyzeCallReturnForF128(ArgsFlags, MF.getFunction().getReturnType());
PreAnalyzeReturnForVectorFloat(ArgsFlags);
bool Return = CCState::CheckReturn(ArgsFlags, Fn);
OriginalArgWasFloat.clear();
Expand All @@ -191,6 +193,16 @@ class MipsCCState : public CCState {
return Return;
}

bool CheckCallReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
CCAssignFn Fn, const Type *RetTy) {
PreAnalyzeCallReturnForF128(ArgsFlags, RetTy);
PreAnalyzeReturnForVectorFloat(ArgsFlags);
Comment on lines +198 to +199
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I don't understand how this fixes it, but this looks like hacking around something that shouldn't require special casing

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Add a new function to check whether call funtion return type was origin from fp128.

bool Return = CCState::CheckReturn(ArgsFlags, Fn);
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
OriginalArgWasFloatVector.clear();
return Return;
}
bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; }
bool WasOriginalArgFloat(unsigned ValNo) {
return OriginalArgWasFloat[ValNo];
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MipsISelLowering.cpp
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Expand Up @@ -3864,10 +3864,10 @@ bool
MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
LLVMContext &Context, const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, RetCC_Mips);
return CCInfo.CheckCallReturn(Outs, RetCC_Mips, RetTy);
}

bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsISelLowering.h
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Expand Up @@ -615,7 +615,7 @@ class TargetRegisterClass;
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Expand Up @@ -7868,7 +7868,8 @@ bool
PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(
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2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -1373,7 +1373,7 @@ namespace llvm {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -20361,7 +20361,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,

bool RISCVTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -762,7 +762,7 @@ class RISCVTargetLowering : public TargetLowering {
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
LLVMContext &Context, const Type *RetTy) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Sparc/SparcISelLowering.cpp
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Expand Up @@ -234,7 +234,8 @@ static unsigned toCallerWindow(unsigned Reg) {

bool SparcTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
const Type *RetTy) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
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