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[AMDGPU] Use the SchedModel available in SIInstrInfo #110859

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Oct 2, 2024
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[AMDGPU] Use the SchedModel available in SIInstrInfo #110859

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7 changes: 3 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
const SIInstrInfo *SII;
const TargetRegisterInfo *TRI;

TargetSchedModel SchedModel;
const TargetSchedModel *SchedModel;

AMDGPUInsertDelayAlu() : MachineFunctionPass(ID) {}

Expand Down Expand Up @@ -387,7 +387,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
if (Type != OTHER) {
// TODO: Scan implicit defs too?
for (const auto &Op : MI.defs()) {
unsigned Latency = SchedModel.computeOperandLatency(
unsigned Latency = SchedModel->computeOperandLatency(
&MI, Op.getOperandNo(), nullptr, 0);
for (MCRegUnit Unit : TRI->regunits(Op.getReg()))
State[Unit] = DelayInfo(Type, Latency);
Expand Down Expand Up @@ -429,8 +429,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {

SII = ST.getInstrInfo();
TRI = ST.getRegisterInfo();

SchedModel.init(&ST);
SchedModel = &SII->getSchedModel();

// Calculate the delay state for each basic block, iterating until we reach
// a fixed point.
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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Expand Up @@ -59,10 +59,10 @@ static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF,
GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF)
: IsHazardRecognizerMode(false), CurrCycleInstr(nullptr), MF(MF),
ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()),
TRI(TII.getRegisterInfo()), UseVALUReadHazardExhaustiveSearch(false),
TRI(TII.getRegisterInfo()), TSchedModel(TII.getSchedModel()),
UseVALUReadHazardExhaustiveSearch(false),
ClauseUses(TRI.getNumRegUnits()), ClauseDefs(TRI.getNumRegUnits()) {
MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5;
TSchedModel.init(&ST);
RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
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Expand Up @@ -46,7 +46,7 @@ class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
const GCNSubtarget &ST;
const SIInstrInfo &TII;
const SIRegisterInfo &TRI;
TargetSchedModel TSchedModel;
const TargetSchedModel &TSchedModel;
bool RunLdsBranchVmemWARHazardFixup;
BitVector VALUReadHazardSGPRs;
bool UseVALUReadHazardExhaustiveSearch;
Expand Down
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