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[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc] #105551

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Aug 29, 2024
Merged

[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc] #105551

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e391739
[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc]
preames Aug 21, 2024
defe77d
Merge branch 'main' into pr-vp-reduce-macros
preames Aug 29, 2024
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19 changes: 0 additions & 19 deletions llvm/include/llvm/IR/VPIntrinsics.def
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Original file line number Diff line number Diff line change
Expand Up @@ -129,11 +129,6 @@
#define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS)
#endif

// Map this VP reduction intrinsic to its reduction operand positions.
#ifndef VP_PROPERTY_REDUCTION
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS)
#endif

// A property to infer VP binary-op SDNode opcodes automatically.
#ifndef VP_PROPERTY_BINARYOP
#define VP_PROPERTY_BINARYOP
Expand All @@ -144,13 +139,6 @@
#define VP_PROPERTY_CASTOP
#endif

// This VP Intrinsic is a comparison operation
// The condition code arg is at CCPOS and accepts floating-point condition
// codes if ISFP is set, else it accepts integer condition codes.
#ifndef VP_PROPERTY_CMP
#define VP_PROPERTY_CMP(CCPOS, ISFP)
#endif

/// } Property Macros

///// Integer Arithmetic {
Expand Down Expand Up @@ -567,15 +555,13 @@ END_REGISTER_VP_SDNODE(VP_SETCC)
BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
VP_PROPERTY_CMP(2, true)
VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp)
END_REGISTER_VP_INTRINSIC(vp_fcmp)

// llvm.vp.icmp(x,y,cc,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
VP_PROPERTY_CMP(2, false)
END_REGISTER_VP_INTRINSIC(vp_icmp)

///// } Comparisons
Expand Down Expand Up @@ -655,7 +641,6 @@ END_REGISTER_VP(vp_gather, VP_GATHER)
BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
VP_PROPERTY_REDUCTION(0, 1) \
END_REGISTER_VP(VPID, VPSD)

// llvm.vp.reduce.add(start,x,mask,vlen)
Expand Down Expand Up @@ -725,13 +710,11 @@ HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM,
#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, SDOPC, SEQ_SDOPC, INTRIN) \
BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
VP_PROPERTY_REDUCTION(0, 1) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
END_REGISTER_VP_SDNODE(VPSD) \
BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SEQ_SDOPC) \
VP_PROPERTY_REDUCTION(0, 1) \
END_REGISTER_VP_SDNODE(SEQ_VPSD) \
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
END_REGISTER_VP_INTRINSIC(VPID)
Expand Down Expand Up @@ -796,11 +779,9 @@ END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT)
#undef HELPER_MAP_VPID_TO_VPSD
#undef VP_PROPERTY_BINARYOP
#undef VP_PROPERTY_CASTOP
#undef VP_PROPERTY_CMP
#undef VP_PROPERTY_CONSTRAINEDFP
#undef VP_PROPERTY_FUNCTIONAL_INTRINSIC
#undef VP_PROPERTY_FUNCTIONAL_OPC
#undef VP_PROPERTY_FUNCTIONAL_SDOPC
#undef VP_PROPERTY_NO_FUNCTIONAL
#undef VP_PROPERTY_MEMOP
#undef VP_PROPERTY_REDUCTION
25 changes: 19 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -503,13 +503,26 @@ bool ISD::isVPBinaryOp(unsigned Opcode) {
bool ISD::isVPReduction(unsigned Opcode) {
switch (Opcode) {
default:
break;
#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
#define END_REGISTER_VP_SDNODE(VPSD) break;
#include "llvm/IR/VPIntrinsics.def"
return false;
case ISD::VP_REDUCE_ADD:
case ISD::VP_REDUCE_MUL:
case ISD::VP_REDUCE_AND:
case ISD::VP_REDUCE_OR:
case ISD::VP_REDUCE_XOR:
case ISD::VP_REDUCE_SMAX:
case ISD::VP_REDUCE_SMIN:
case ISD::VP_REDUCE_UMAX:
case ISD::VP_REDUCE_UMIN:
case ISD::VP_REDUCE_FMAX:
case ISD::VP_REDUCE_FMIN:
case ISD::VP_REDUCE_FMAXIMUM:
case ISD::VP_REDUCE_FMINIMUM:
case ISD::VP_REDUCE_FADD:
case ISD::VP_REDUCE_FMUL:
case ISD::VP_REDUCE_SEQ_FADD:
case ISD::VP_REDUCE_SEQ_FMUL:
return true;
}
return false;
}

/// The operand position of the vector mask.
Expand Down
73 changes: 29 additions & 44 deletions llvm/lib/IR/IntrinsicInst.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -738,14 +738,25 @@ Function *VPIntrinsic::getDeclarationForParams(Module *M, Intrinsic::ID VPID,

bool VPReductionIntrinsic::isVPReduction(Intrinsic::ID ID) {
switch (ID) {
case Intrinsic::vp_reduce_add:
case Intrinsic::vp_reduce_mul:
case Intrinsic::vp_reduce_and:
case Intrinsic::vp_reduce_or:
case Intrinsic::vp_reduce_xor:
case Intrinsic::vp_reduce_smax:
case Intrinsic::vp_reduce_smin:
case Intrinsic::vp_reduce_umax:
case Intrinsic::vp_reduce_umin:
case Intrinsic::vp_reduce_fmax:
case Intrinsic::vp_reduce_fmin:
case Intrinsic::vp_reduce_fmaximum:
case Intrinsic::vp_reduce_fminimum:
case Intrinsic::vp_reduce_fadd:
case Intrinsic::vp_reduce_fmul:
return true;
default:
break;
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
#define END_REGISTER_VP_INTRINSIC(VPID) break;
#include "llvm/IR/VPIntrinsics.def"
return false;
}
return false;
}

bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
Expand All @@ -763,13 +774,11 @@ bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
bool VPCmpIntrinsic::isVPCmp(Intrinsic::ID ID) {
switch (ID) {
default:
break;
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
#define VP_PROPERTY_CMP(CCPOS, ...) return true;
#define END_REGISTER_VP_INTRINSIC(VPID) break;
#include "llvm/IR/VPIntrinsics.def"
return false;
case Intrinsic::vp_fcmp:
case Intrinsic::vp_icmp:
return true;
}
return false;
}

bool VPBinOpIntrinsic::isVPBinOp(Intrinsic::ID ID) {
Expand Down Expand Up @@ -803,22 +812,10 @@ static ICmpInst::Predicate getIntPredicateFromMD(const Value *Op) {
}

CmpInst::Predicate VPCmpIntrinsic::getPredicate() const {
bool IsFP = true;
std::optional<unsigned> CCArgIdx;
switch (getIntrinsicID()) {
default:
break;
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
#define VP_PROPERTY_CMP(CCPOS, ISFP) \
CCArgIdx = CCPOS; \
IsFP = ISFP; \
break;
#define END_REGISTER_VP_INTRINSIC(VPID) break;
#include "llvm/IR/VPIntrinsics.def"
}
assert(CCArgIdx && "Unexpected vector-predicated comparison");
return IsFP ? getFPPredicateFromMD(getArgOperand(*CCArgIdx))
: getIntPredicateFromMD(getArgOperand(*CCArgIdx));
assert(isVPCmp(getIntrinsicID()));
return getIntrinsicID() == Intrinsic::vp_fcmp
? getFPPredicateFromMD(getArgOperand(2))
: getIntPredicateFromMD(getArgOperand(2));
}

unsigned VPReductionIntrinsic::getVectorParamPos() const {
Expand All @@ -831,27 +828,15 @@ unsigned VPReductionIntrinsic::getStartParamPos() const {

std::optional<unsigned>
VPReductionIntrinsic::getVectorParamPos(Intrinsic::ID ID) {
switch (ID) {
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return VECTORPOS;
#define END_REGISTER_VP_INTRINSIC(VPID) break;
#include "llvm/IR/VPIntrinsics.def"
default:
break;
}
if (isVPReduction(ID))
return 1;
return std::nullopt;
}

std::optional<unsigned>
VPReductionIntrinsic::getStartParamPos(Intrinsic::ID ID) {
switch (ID) {
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return STARTPOS;
#define END_REGISTER_VP_INTRINSIC(VPID) break;
#include "llvm/IR/VPIntrinsics.def"
default:
break;
}
if (isVPReduction(ID))
return 0;
return std::nullopt;
}

Expand Down
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