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[RISCV] Add sifive-p470 processor (#102022)
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This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate
vector scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.
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@michaelmaitland
michaelmaitland authored Aug 7, 2024
1 parent e3778a5 commit 0c25f85
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48 changes: 48 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Expand Up @@ -304,6 +304,54 @@
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"

// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s
// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+a"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+f"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+d"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+v"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt"
// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"

// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s
// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
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5 changes: 3 additions & 2 deletions clang/test/Misc/target-invalid-cpu-note.c
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Expand Up @@ -85,12 +85,13 @@

// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}

// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, generic, rocket, sifive-7-series{{$}}

// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -107,6 +107,7 @@ Changes to the RISC-V Backend
the required alignment space with a sequence of `0x0` bytes (the requested
fill value) rather than NOPs.
* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
* ``-mcpu=sifive-p470`` was added.

Changes to the WebAssembly Backend
----------------------------------
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31 changes: 26 additions & 5 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -239,6 +239,12 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
FeatureStdExtZbb],
SiFiveX280TuneFeatures>;

defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
TuneConditionalCompressedMoveFusion,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion,
FeaturePostRAScheduler];

def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
[Feature64Bit,
FeatureStdExtI,
Expand Down Expand Up @@ -266,11 +272,26 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
FeatureStdExtZfhmin,
FeatureUnalignedScalarMem,
FeatureUnalignedVectorMem],
[TuneNoDefaultUnroll,
TuneConditionalCompressedMoveFusion,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion,
FeaturePostRAScheduler]>;
SiFiveP400TuneFeatures>;

def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
!listconcat(RVA22U64Features,
[FeatureStdExtV,
FeatureStdExtZifencei,
FeatureStdExtZihintntl,
FeatureStdExtZvl128b,
FeatureStdExtZvbb,
FeatureStdExtZvknc,
FeatureStdExtZvkng,
FeatureStdExtZvksc,
FeatureStdExtZvksg,
FeatureVendorXSiFivecdiscarddlone,
FeatureVendorXSiFivecflushdlone,
FeatureUnalignedScalarMem,
FeatureUnalignedVectorMem]),
!listconcat(SiFiveP400TuneFeatures,
[TuneNoSinkSplatOperands])>;


def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
[Feature64Bit,
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