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[CIR][CIRGen][Neon] Make vrnda emit RoundOp directly #1453

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Merged
merged 2 commits into from
Mar 7, 2025
Merged

[CIR][CIRGen][Neon] Make vrnda emit RoundOp directly #1453

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f3ff95f
[CIR][CIRGen][Neon] Make vrnda emit RoundOp directly
FantasqueX Mar 7, 2025
c7a747d
Fix test
FantasqueX Mar 7, 2025
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4 changes: 2 additions & 2 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4135,8 +4135,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vrnda_v:
case NEON::BI__builtin_neon_vrndaq_v: {
assert(!cir::MissingFeatures::emitConstrainedFPCall());
return emitNeonCall(builder, {ty}, Ops, "round", ty,
getLoc(E->getExprLoc()));
return emitNeonCallToOp<cir::RoundOp>(builder, {ty}, Ops, std::nullopt, ty,
getLoc(E->getExprLoc()));
}
case NEON::BI__builtin_neon_vrndih_f16: {
llvm_unreachable("NEON::BI__builtin_neon_vrndih_f16 NYI");
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4 changes: 2 additions & 2 deletions clang/test/CIR/CodeGen/AArch64/neon-arith.c
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Expand Up @@ -47,7 +47,7 @@ float32x2_t test_vrnda_f32(float32x2_t a) {
// CIR: [[INTRIN_ARG:%.*]] = cir.load [[ARG_SAVE]] : !cir.ptr<!cir.vector<!cir.float x 2>>, !cir.vector<!cir.float x 2>
// CIR: [[INTRIN_ARG_CAST:%.*]] = cir.cast(bitcast, [[INTRIN_ARG]] : !cir.vector<!cir.float x 2>), !cir.vector<!s8i x 8>
// CIR: [[INTRIN_ARG_BACK:%.*]] = cir.cast(bitcast, [[INTRIN_ARG_CAST]] : !cir.vector<!s8i x 8>), !cir.vector<!cir.float x 2>
// CIR: {{%.*}} = cir.llvm.intrinsic "round" [[INTRIN_ARG_BACK]] : (!cir.vector<!cir.float x 2>) -> !cir.vector<!cir.float x 2>
// CIR: {{%.*}} = cir.round [[INTRIN_ARG_BACK]] : !cir.vector<!cir.float x 2>
// CIR: cir.return {{%.*}} : !cir.vector<!cir.float x 2>

// CIR-LABEL: test_vrnda_f32
Expand All @@ -71,7 +71,7 @@ float32x4_t test_vrndaq_f32(float32x4_t a) {
// CIR: [[INTRIN_ARG:%.*]] = cir.load [[ARG_SAVE]] : !cir.ptr<!cir.vector<!cir.float x 4>>, !cir.vector<!cir.float x 4>
// CIR: [[INTRIN_ARG_CAST:%.*]] = cir.cast(bitcast, [[INTRIN_ARG]] : !cir.vector<!cir.float x 4>), !cir.vector<!s8i x 16>
// CIR: [[INTRIN_ARG_BACK:%.*]] = cir.cast(bitcast, [[INTRIN_ARG_CAST]] : !cir.vector<!s8i x 16>), !cir.vector<!cir.float x 4>
// CIR: {{%.*}} = cir.llvm.intrinsic "round" [[INTRIN_ARG_BACK]] : (!cir.vector<!cir.float x 4>) -> !cir.vector<!cir.float x 4>
// CIR: {{%.*}} = cir.round [[INTRIN_ARG_BACK]] : !cir.vector<!cir.float x 4>
// CIR: cir.return {{%.*}} : !cir.vector<!cir.float x 4>

// LLVM: {{.*}}test_vrndaq_f32(<4 x float>{{.*}}[[ARG:%.*]])
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