changes based on review; add conversion and emitter tests

llvm · Oct 31, 2024 · cebc29e · cebc29e
1 parent ca934b3
commit cebc29e
Show file tree

Hide file tree

Showing 4 changed files with 87 additions and 16 deletions.
diff --git a/lib/Dialect/Calyx/Export/CalyxEmitter.cpp b/lib/Dialect/Calyx/Export/CalyxEmitter.cpp
@@ -981,21 +981,28 @@ void Emitter::emitLibraryFloatingPoint(Operation *op) {
   // sigWidth. See
   // http://www.jhauser.us/arithmetic/HardFloat-1/doc/HardFloat-Verilog.html
   unsigned expWidth, sigWidth;
-  if (bitWidth == 16) {
+  switch (bitWidth) {
+  case 16:
     expWidth = 5;
     sigWidth = 11;
-  } else if (bitWidth == 32) {
+    break;
+  case 32:
     expWidth = 8;
     sigWidth = 24;
-  } else if (bitWidth == 64) {
+    break;
+  case 64:
     expWidth = 11;
     sigWidth = 53;
-  } else if (bitWidth == 128) {
+    break;
+  case 128:
     expWidth = 15;
     sigWidth = 113;
-  } else {
-    op->emitError("Unsupported floating point width");
+    break;
+  default:
+    op->emitError("The supported bitwidths are 16, 32, 64, and 128");
+    return;
   }
+
   StringRef opName = op->getName().getStringRef();
   indent() << getAttributes(op, /*atFormat=*/true) << cell.instanceName()
            << space() << equals() << space() << removeCalyxPrefix(opName)

diff --git a/test/Conversion/SCFToCalyx/convert_simple.mlir b/test/Conversion/SCFToCalyx/convert_simple.mlir
@@ -233,3 +233,27 @@ module {
     return %arg0, %0, %1 : f32, i32, f32
   }
 }
+
+// -----
+
+// Test floating point add
+
+// CHECK:             calyx.group @bb0_0 {
+// CHECK-DAG:               calyx.assign %std_addFN_0.left = %in0 : f32
+// CHECK-DAG:               calyx.assign %std_addFN_0.right = %cst : f32
+// CHECK-DAG:               calyx.assign %addf_0_reg.in = %std_addFN_0.out : f32
+// CHECK-DAG:               calyx.assign %addf_0_reg.write_en = %std_addFN_0.done : i1
+// CHECK-DAG:               %0 = comb.xor %std_addFN_0.done, %true : i1
+// CHECK-DAG:               calyx.assign %std_addFN_0.go = %0 ? %true : i1
+// CHECK-DAG:               calyx.assign %std_addFN_0.subOp = %false : i1
+// CHECK-DAG:               calyx.group_done %addf_0_reg.done : i1
+// CHECK-DAG:             }
+
+module {
+  func.func @main(%arg0 : f32) -> f32 {
+    %0 = arith.constant 4.2 : f32
+    %1 = arith.addf %arg0, %0 : f32
+
+    return %1 : f32
+  }
+}
diff --git a/test/Conversion/SCFToCalyx/errors.mlir b/test/Conversion/SCFToCalyx/errors.mlir
@@ -1,15 +1,5 @@
 // RUN: circt-opt --lower-scf-to-calyx %s -split-input-file -verify-diagnostics
 
-module {
-  func.func @f(%arg0 : f32, %arg1 : f32) -> f32 {
-    // expected-error @+1 {{failed to legalize operation 'arith.addf' that was explicitly marked illegal}}
-    %2 = arith.addf %arg0, %arg1 : f32
-    return %2 : f32
-  }
-}
-
-// -----
-
 // expected-error @+1 {{Module contains multiple functions, but no top level function was set. Please see --top-level-function}}
 module {
   func.func @f1() {

diff --git a/test/Dialect/Calyx/emit.mlir b/test/Dialect/Calyx/emit.mlir
@@ -280,3 +280,53 @@ module attributes {calyx.entrypoint = "main"} {
   } {toplevel}
 }
 
+
+// -----
+
+module attributes {calyx.entrypoint = "main"} {
+  calyx.component @main(%in0: f32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%out0: f32, %done: i1 {done}) {
+    // CHECK:           std_addFN_0 = std_addFN(8, 24, 32);
+    %cst = calyx.constant {sym_name = "cst_0"} 4.200000e+00 : f32
+    %true = hw.constant true
+    %false = hw.constant false
+    %addf_0_reg.in, %addf_0_reg.write_en, %addf_0_reg.clk, %addf_0_reg.reset, %addf_0_reg.out, %addf_0_reg.done = calyx.register @addf_0_reg : f32, i1, i1, i1, f32, i1
+    %std_addFN_0.clk, %std_addFN_0.reset, %std_addFN_0.go, %std_addFN_0.control, %std_addFN_0.subOp, %std_addFN_0.left, %std_addFN_0.right, %std_addFN_0.roundingMode, %std_addFN_0.out, %std_addFN_0.execptionalFlags, %std_addFN_0.done = calyx.std_addFN @std_addFN_0 : i1, i1, i1, i1, i1, f32, f32, i3, f32, i5, i1
+    %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : f32, i1, i1, i1, f32, i1
+    calyx.wires {
+      calyx.assign %out0 = %ret_arg0_reg.out : f32
+
+      // CHECK-LABEL: group bb0_0 {
+      // CHECK-NEXT:    std_addFN_0.left = in0;
+      // CHECK-NEXT:    std_addFN_0.right = cst_0.out;
+      // CHECK-NEXT:    addf_0_reg.in = std_addFN_0.out;
+      // CHECK-NEXT:    addf_0_reg.write_en = std_addFN_0.done;
+      // CHECK-NEXT:    std_addFN_0.go = !std_addFN_0.done ? 1'd1;
+      // CHECK-NEXT:    std_addFN_0.subOp = 1'd0;
+      // CHECK-NEXT:    bb0_0[done] = addf_0_reg.done;
+      // CHECK-NEXT:  }
+      calyx.group @bb0_0 {
+        calyx.assign %std_addFN_0.left = %in0 : f32
+        calyx.assign %std_addFN_0.right = %cst : f32
+        calyx.assign %addf_0_reg.in = %std_addFN_0.out : f32
+        calyx.assign %addf_0_reg.write_en = %std_addFN_0.done : i1
+        %0 = comb.xor %std_addFN_0.done, %true : i1
+        calyx.assign %std_addFN_0.go = %0 ? %true : i1
+        calyx.assign %std_addFN_0.subOp = %false : i1
+        calyx.group_done %addf_0_reg.done : i1
+      }
+      calyx.group @ret_assign_0 {
+        calyx.assign %ret_arg0_reg.in = %std_addFN_0.out : f32
+        calyx.assign %ret_arg0_reg.write_en = %true : i1
+        calyx.group_done %ret_arg0_reg.done : i1
+      }
+    }
+    calyx.control {
+      calyx.seq {
+        calyx.seq {
+          calyx.enable @bb0_0
+          calyx.enable @ret_assign_0
+        }
+      }
+    }
+  } {toplevel}
+}