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Issue 578 #579

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merged 5 commits into from
Feb 28, 2022
Merged

Issue 578 #579

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359ec15
Expose DR registers, and make the instruction lifter invent global va…
pgoodman Feb 28, 2022
6e59598
Bug fix
pgoodman Feb 28, 2022
0485de3
Bug fix
pgoodman Feb 28, 2022
119554c
Address review comments
pgoodman Feb 28, 2022
7494b0b
Address review comments
pgoodman Feb 28, 2022
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68 changes: 42 additions & 26 deletions lib/Arch/SPARC64/Extract.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1934,28 +1934,44 @@ static bool TryDecodeOpf54(Instruction &inst, uint32_t bits) {
}

// Logical Operations
DEFINE_TryDecode(AND) DEFINE_TryDecode(ANDcc) DEFINE_TryDecode(ANDN)
DEFINE_TryDecode(ANDNcc)

DEFINE_TryDecode(OR) DEFINE_TryDecode(ORcc) DEFINE_TryDecode(ORN)
DEFINE_TryDecode(ORNcc)

DEFINE_TryDecode(XOR) DEFINE_TryDecode(XORcc)
DEFINE_TryDecode(XNOR) DEFINE_TryDecode(XNORcc)

// Binary Operations
DEFINE_TryDecode(ADD) DEFINE_TryDecode(ADDC) DEFINE_TryDecode(
ADDcc) DEFINE_TryDecode(ADDCcc)

DEFINE_TryDecode(SUB) DEFINE_TryDecode(SUBC) DEFINE_TryDecode(
SUBcc) DEFINE_TryDecode(SUBCcc)

DEFINE_TryDecode(UMUL) DEFINE_TryDecode(SMUL) DEFINE_TryDecode(MULX)
DEFINE_TryDecode(UMULcc) DEFINE_TryDecode(SMULcc)

DEFINE_TryDecode(UDIV) DEFINE_TryDecode(SDIV)
DEFINE_TryDecode(UDIVX) DEFINE_TryDecode(SDIVX)
DEFINE_TryDecode(UDIVcc) DEFINE_TryDecode(SDIVcc)
DEFINE_TryDecode(AND)
DEFINE_TryDecode(ANDcc)
DEFINE_TryDecode(ANDN)
DEFINE_TryDecode(ANDNcc)

DEFINE_TryDecode(OR)
DEFINE_TryDecode(ORcc)
DEFINE_TryDecode(ORN)
DEFINE_TryDecode(ORNcc)

DEFINE_TryDecode(XOR)
DEFINE_TryDecode(XORcc)
DEFINE_TryDecode(XNOR)
DEFINE_TryDecode(XNORcc)

// Binary Operations
DEFINE_TryDecode(ADD)
DEFINE_TryDecode(ADDC)
DEFINE_TryDecode(ADDcc)
DEFINE_TryDecode(ADDCcc)

DEFINE_TryDecode(SUB)
DEFINE_TryDecode(SUBC)
DEFINE_TryDecode(SUBcc)
DEFINE_TryDecode(SUBCcc)

DEFINE_TryDecode(UMUL)
DEFINE_TryDecode(SMUL)
DEFINE_TryDecode(MULX)
DEFINE_TryDecode(UMULcc)
DEFINE_TryDecode(SMULcc)

DEFINE_TryDecode(UDIV)
DEFINE_TryDecode(SDIV)
DEFINE_TryDecode(UDIVX)
DEFINE_TryDecode(SDIVX)
DEFINE_TryDecode(UDIVcc)
DEFINE_TryDecode(SDIVcc)

#undef DEFINE_TryDecode
#define DEFINE_TryDecode(ins) \
Expand All @@ -1967,10 +1983,10 @@ DEFINE_TryDecode(AND) DEFINE_TryDecode(ANDcc) DEFINE_TryDecode(ANDN)
return true; \
}

DEFINE_TryDecode(TADDcc)
DEFINE_TryDecode(TSUBcc)
DEFINE_TryDecode(TADDccTV)
DEFINE_TryDecode(TSUBccTV)
DEFINE_TryDecode(TADDcc)
DEFINE_TryDecode(TSUBcc)
DEFINE_TryDecode(TADDccTV)
DEFINE_TryDecode(TSUBccTV)

#undef DEFINE_TryDecode

Expand Down
1 change: 0 additions & 1 deletion lib/Arch/X86/Arch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1752,7 +1752,6 @@ void X86Arch::FinishLiftedFunctionInitialization(

(void) this->RegisterByName("PC")->AddressOf(state_ptr_arg, ir);


if (64 == address_size) {
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "CSBASE"));
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "SSBASE"));
Expand Down
12 changes: 6 additions & 6 deletions lib/Arch/X86/Runtime/BasicBlock.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37,12 +37,12 @@ extern uint64_t DR6;
extern uint64_t DR7;

// Control regs.
extern CR0Reg gCR0;
extern CR1Reg gCR1;
extern CR2Reg gCR2;
extern CR3Reg gCR3;
extern CR4Reg gCR4;
extern CR8Reg gCR8;
extern CR0Reg CR0;
extern CR1Reg CR1;
extern CR2Reg CR2;
extern CR3Reg CR3;
extern CR4Reg CR4;
extern CR8Reg CR8;

#pragma clang diagnostic pop

Expand Down
33 changes: 20 additions & 13 deletions lib/BC/InstructionLifter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -231,6 +231,7 @@ InstructionLifter::LoadRegAddress(llvm::BasicBlock *block,
llvm::Value *state_ptr,
std::string_view reg_name_) const {
const auto func = block->getParent();
const auto module = func->getParent();

// Invalidate the cache.
if (func != impl->last_func) {
Expand Down Expand Up @@ -290,9 +291,25 @@ InstructionLifter::LoadRegAddress(llvm::BasicBlock *block,
reg_ptr_it->second = reg_ptr;
return reg_ptr;

// Try to find it as a global variable.
} else if (auto gvar = module->getGlobalVariable(reg_name)) {
return gvar;

// Invent a fake one and keep going.
} else {
LOG(FATAL) << "Could not locate variable or register " << reg_name_;
return nullptr;
std::stringstream unk_var;
unk_var << "__remill_unknown_register_" << reg_name;
auto unk_var_name = unk_var.str();
auto var = module->getGlobalVariable(unk_var_name);
if (!var) {
LOG(ERROR)
<< "Could not locate variable or register " << reg_name_;

var = new llvm::GlobalVariable(
*module, impl->word_type, false, llvm::GlobalValue::ExternalLinkage,
llvm::UndefValue::get(impl->word_type), unk_var_name);
}
return var;
}
}

Expand Down Expand Up @@ -563,12 +580,7 @@ llvm::Value *InstructionLifter::LiftRegisterOperand(Instruction &inst,
<< "Expected " << arch_reg.name << " to be an integral type "
<< "for instruction at " << std::hex << inst.pc;

CHECK(word_size == arg_size)
<< "Expected integer argument to be machine word size ("
<< word_size << " bits) but is is " << arg_size << " instead "
<< "in instruction at " << std::hex << inst.pc;

val = new llvm::ZExtInst(val, impl->word_type,
val = new llvm::ZExtInst(val, arg_type,
llvm::Twine::createNull(), block);

} else if (arg_type->isFloatingPointTy()) {
Expand All @@ -586,11 +598,6 @@ llvm::Value *InstructionLifter::LiftRegisterOperand(Instruction &inst,
<< "Expected " << arch_reg.name << " to be an integral type "
<< "for instruction at " << std::hex << inst.pc;

CHECK(word_size == arg_size)
<< "Expected integer argument to be machine word size ("
<< word_size << " bits) but is is " << arg_size << " instead "
<< "in instruction at " << std::hex << inst.pc;

val = new llvm::TruncInst(val, arg_type, llvm::Twine::createNull(),
block);

Expand Down