if run at 240MHz (CPU) delay needs to be bigger

liebman · Oct 25, 2024 · fcecfef · fcecfef
1 parent 647f2e0
commit fcecfef
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/esp-hal/src/i2s_parallel.rs b/esp-hal/src/i2s_parallel.rs
@@ -622,7 +622,7 @@ pub trait Instance: Signals + RegBlock {
     fn tx_reset(&self) {
         let r = self.register_block();
         r.conf().modify(|_, w| w.tx_reset().set_bit());
-        xtensa_lx::timer::delay(20);
+        xtensa_lx::timer::delay(100);
         r.conf().modify(|_, w| w.tx_reset().clear_bit());
     }