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lauchinyuan/README.md

Hi there 👋

  • 🌱 I’m currently focusing on ASIC design.
  • 🔭 I obtained my bachelor's degree from Shenzhen University, and I am currently pursuing a master's degree at Zhengzhou University.
  • 🏢 I interned at the Beijing Institute of Open Source Chip from 2023 to 2024 as a Digital IC Design and Verification Engineer, focusing on DDR Subsystem.
  • 📫 How to reach me: lauchinyuan@yeah.net or 2018133098@email.szu.edu.cn

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  1. FPGA_QPSK-modem FPGA_QPSK-modem Public

    A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

    Verilog 118 28

  2. Booth4_wallace_MULT16_16 Booth4_wallace_MULT16_16 Public

    A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction

    Verilog 35 4

  3. FPGA_DDR3_Ctrl FPGA_DDR3_Ctrl Public

    An AXI DDR3 SDRAM controller for FPGA

    Verilog 28 6

  4. Asymmetric_async_FIFO Asymmetric_async_FIFO Public

    asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.

    Verilog 15 4

  5. tinyRV32 tinyRV32 Public

    A simple RISC-V core

    Verilog 1

  6. Pytorch_NN_Quant_to_FPGA Pytorch_NN_Quant_to_FPGA Public

    Using pytorch to realize neural network quantization, parameter export and FPGA/ASIC fixed-point arithemetic simulation

    Python 6 4