Renumber ops

hw/verilog/tenyr.v

@@ -56,14 +56,14 @@ module Exec(input clk, en, output reg done, output reg[31:0] valZ,
         { rop , valZ , rA   , rB   , rC   , done , add , act    , staged } <=
         { op  , rZ   , valA , valB , valC , add  , act , staged , en     } ;
         if (staged) case (rop)
-            4'b0000: rY <=  (rA  |  rB  ); 4'b1000: rY <= -(rA  >= rB);
-            4'b0001: rY <=  (rA  &  rB  ); 4'b1001: rY <=  (rA  &~ rB);
-            4'b0010: rY <=  (rA  +  rB  ); 4'b1010: rY <=  (rA  ^  rB);
-            4'b0011: rY <=  (rA  *  rB  ); 4'b1011: rY <=  (rA  -  rB);
-            4'b0100: rY <=  {rA,rB[11:0]}; 4'b1100: rY <=  (rA  |~ rB);
-            4'b0101: rY <=  (rA  << rB  ); 4'b1101: rY <=  (rA  >> rB);
-            4'b0110: rY <= -(rA  <  rB  ); 4'b1110: rY <= -(!(!(rA & (1 << rB))));
-            4'b0111: rY <= -(rA  == rB  ); 4'b1111: rY <=  (rA >>> rB);
+            4'h0: rY <=  (rA  |  rB); 4'h8: rY <=  (rA  |~ rB  );
+            4'h1: rY <=  (rA  &  rB); 4'h9: rY <=  (rA  &~ rB  );
+            4'h2: rY <=  (rA  ^  rB); 4'ha: rY <=  {rA,rB[11:0]};
+            4'h3: rY <=  (rA >>> rB); 4'hb: rY <=  (rA  >> rB  );
+            4'h4: rY <=  (rA  +  rB); 4'hc: rY <=  (rA  -  rB  );
+            4'h5: rY <=  (rA  *  rB); 4'hd: rY <=  (rA  << rB  );
+            4'h6: rY <= -(rA  == rB); 4'he: rY <= -(!(!(rA & (1 << rB))));
+            4'h7: rY <= -(rA  <  rB); 4'hf: rY <= -(rA  >= rB  );
         endcase
         if (act) rZ <= rY + rC;
     end

src/ops.h

@@ -104,23 +104,34 @@ struct element_list {
     struct element_list *prev, *next;
 };
 
+/*
+ * Operations are encoded this way to group hardware-similar operations
+ * together, differing by the most sigificant bit only.
+ *
+ * In the table below, the column header is read before the row ; e.g., `&` is
+ * 0b0001 and `-` is 0b1100.
+ *
+ *       0   1
+ * 000   |   |~
+ * 001   &   &~
+ * 010   ^   ^^
+ * 011   >>  >>>
+ * 100   +   -
+ * 101   *   <<
+ * 110   ==  @
+ * 111   <   >=
+ */
+
 enum op {
-    OP_BITWISE_OR        = 0x0,
-    OP_BITWISE_AND       = 0x1,
-    OP_ADD               = 0x2,
-    OP_MULTIPLY          = 0x3,
-    OP_PACK              = 0x4,
-    OP_SHIFT_LEFT        = 0x5,
-    OP_COMPARE_LT        = 0x6,
-    OP_COMPARE_EQ        = 0x7,
-    OP_COMPARE_GE        = 0x8,
-    OP_BITWISE_ANDN      = 0x9,
-    OP_BITWISE_XOR       = 0xa,
-    OP_SUBTRACT          = 0xb,
-    OP_BITWISE_ORN       = 0xc,
-    OP_SHIFT_RIGHT_LOGIC = 0xd,
-    OP_TEST_BIT          = 0xe,
-    OP_SHIFT_RIGHT_ARITH = 0xf,
+    OP_BITWISE_OR        = 0x0,	OP_BITWISE_ORN       = 0x8,
+    OP_BITWISE_AND       = 0x1,	OP_BITWISE_ANDN      = 0x9,
+    OP_BITWISE_XOR       = 0x2,	OP_PACK              = 0xa,
+    OP_SHIFT_RIGHT_ARITH = 0x3,	OP_SHIFT_RIGHT_LOGIC = 0xb,
+
+    OP_ADD               = 0x4, OP_SUBTRACT          = 0xc,
+    OP_MULTIPLY          = 0x5, OP_SHIFT_LEFT        = 0xd,
+    OP_COMPARE_EQ        = 0x6, OP_TEST_BIT          = 0xe,
+    OP_COMPARE_LT        = 0x7, OP_COMPARE_GE        = 0xf,
 };
 
 #endif