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Merge pull request rust-lang#29 from gnzlbg/arm_intrinsics
[arm] bitwise manipulation instructions
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@@ -15,7 +15,7 @@ debug = true | |
opt-level = 3 | ||
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[profile.bench] | ||
debug = 1 | ||
debug = true | ||
opt-level = 3 | ||
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[dev-dependencies] | ||
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//! ARM intrinsics. | ||
pub use self::v6::*; | ||
pub use self::v7::*; | ||
#[cfg(target_arch = "aarch64")] | ||
pub use self::v8::*; | ||
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mod v6; | ||
mod v7; | ||
#[cfg(target_arch = "aarch64")] | ||
mod v8; |
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//! ARMv6 intrinsics. | ||
//! | ||
//! The reference is [ARMv6-M Architecture Reference | ||
//! Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0419c/index.html). | ||
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/// Reverse the order of the bytes. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rev))] | ||
pub fn _rev_u8(x: u8) -> u8 { | ||
x.swap_bytes() as u8 | ||
} | ||
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/// Reverse the order of the bytes. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rev))] | ||
pub fn _rev_u16(x: u16) -> u16 { | ||
x.swap_bytes() as u16 | ||
} | ||
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/// Reverse the order of the bytes. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rev))] | ||
pub fn _rev_u32(x: u32) -> u32 { | ||
x.swap_bytes() as u32 | ||
} |
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//! ARMv7 intrinsics. | ||
//! | ||
//! The reference is [ARMv7-M Architecture Reference Manual (Issue | ||
//! E.b)](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.b/index.html). | ||
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pub use super::v6::*; | ||
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/// Count Leading Zeros. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _clz_u8(x: u8) -> u8 { | ||
x.leading_zeros() as u8 | ||
} | ||
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/// Count Leading Zeros. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _clz_u16(x: u16) -> u16 { | ||
x.leading_zeros() as u16 | ||
} | ||
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/// Count Leading Zeros. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _clz_u32(x: u32) -> u32 { | ||
x.leading_zeros() as u32 | ||
} | ||
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#[allow(dead_code)] | ||
extern "C" { | ||
#[link_name="llvm.bitreverse.i32"] | ||
fn rbit_u32(i: i32) -> i32; | ||
} | ||
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/// Reverse the bit order. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rbit))] | ||
pub fn _rbit_u32(x: u32) -> u32 { | ||
unsafe { rbit_u32(x as i32) as u32 } | ||
} |
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//! ARMv8 intrinsics. | ||
//! | ||
//! The reference is [ARMv8-A Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.k_10775/index.html). | ||
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pub use super::v7::*; | ||
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/// Reverse the order of the bytes. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rev))] | ||
pub fn _rev_u64(x: u64) -> u64 { | ||
x.swap_bytes() as u64 | ||
} | ||
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/// Count Leading Zeros. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _clz_u64(x: u64) -> u64 { | ||
x.leading_zeros() as u64 | ||
} | ||
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#[allow(dead_code)] | ||
extern "C" { | ||
#[link_name="llvm.bitreverse.i64"] | ||
fn rbit_u64(i: i64) -> i64; | ||
} | ||
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/// Reverse the bit order. | ||
#[inline(always)] | ||
#[cfg_attr(test, assert_instr(rbit))] | ||
pub fn _rbit_u64(x: u64) -> u64 { | ||
unsafe { rbit_u64(x as i64) as u64 } | ||
} | ||
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/// Counts the leading most significant bits set. | ||
/// | ||
/// When all bits of the operand are set it returns the size of the operand in | ||
/// bits. | ||
#[inline(always)] | ||
// LLVM Bug (should be cls): https://bugs.llvm.org/show_bug.cgi?id=31802 | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _cls_u32(x: u32) -> u32 { | ||
u32::leading_zeros(!x) as u32 | ||
} | ||
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/// Counts the leading most significant bits set. | ||
/// | ||
/// When all bits of the operand are set it returns the size of the operand in | ||
/// bits. | ||
#[inline(always)] | ||
// LLVM Bug (should be cls): https://bugs.llvm.org/show_bug.cgi?id=31802 | ||
#[cfg_attr(test, assert_instr(clz))] | ||
pub fn _cls_u64(x: u64) -> u64 { | ||
u64::leading_zeros(!x) as u64 | ||
} |
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