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Allow 16 bit floating point operand for LLVM_AtomicRMWOp
As far as AMDGPU target supports vectorization for atomic_rmw operation, allow construction of LLVM_AtomicRMWOp with 16 bit floating point values. See also: llvm#94845, llvm#95393, llvm#95394 Signed-off-by: Ilya Veselov <iveselov.nn@gmail.com>
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