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jotego · Apr 17, 2017 · 1e796fa · 1e796fa
1 parent 2e878a0
commit 1e796fa
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Showing 7 changed files with 3,372 additions and 21 deletions.
diff --git a/hdl/jt51.v b/hdl/jt51.v
@@ -31,7 +31,7 @@ module jt51(
 	output 				ct1,
 	output 				ct2,
 	output 				irq_n,	// I do not synchronize this signal
-	output		 		p1,
+	output	reg	 		p1,
 	// Low resolution output (same as real chip)
 	output				sample,	// marks new output sample
 	output	signed	[15:0] left,
@@ -44,7 +44,6 @@ module jt51(
 	output	[15:0] dacright
 );
 
-reg p1 /*verilator clocker*/;
 reg rst_p1, rst_p1_aux;
 
 assign dacleft  = { ~xleft [15],  xleft[14:0] };

diff --git a/hdl/jt51_eg.v b/hdl/jt51_eg.v
@@ -61,10 +61,8 @@ parameter ATTACK=2'd0, DECAY1=2'd1, DECAY2=2'd2, RELEASE=2'd3;
 reg		[4:0]	d1level_II;
 reg		[2:0]	cnt_V;
 reg		[5:0]	rate_IV;
-wire	[6:0]	tl_VII;
-wire	[1:0]	ams_VII;
-wire			amsen_VII;
-reg		[9:0]	eg_VI, eg_VII, eg_VIII;
+wire	[9:0]	eg_VI;
+reg		[9:0]	eg_VII, eg_VIII;
 wire	[9:0]	eg_II;
 reg		[11:0]	sum_eg_tl_VII;
 
@@ -102,7 +100,6 @@ wire			cnt_out; // = all_cnt_last[3*31-1:3*30];
 
 reg		[6:0]	pre_rate_III;
 reg		[4:0]	cfg_III;
-wire	[1:0]	ks_III;
 
 always @(*) begin : pre_rate_calc
 	if( cfg_III == 5'd0 )

diff --git a/hdl/jt51_reg.v b/hdl/jt51_reg.v
@@ -42,7 +42,7 @@ module jt51_reg(
 	input			csm,
 	input			overflow_A,
 
-	output			busy,
+	output	reg		busy,
 	output	[1:0]	rl_I,
 	output	[2:0]	fb_II,
 	output	[2:0]	con_I,
@@ -118,7 +118,6 @@ wire up = 	up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
 			up_ks | up_amsen | up_dt2 | up_d1l | up_keyon;
 
 reg	[4:0]	cur;
-reg			busy;
 
 assign cur_op = cur[4:3];
 

diff --git a/syn/xilinx/contra_snd/doc/ymplayer_map history.txt b/syn/xilinx/contra_snd/doc/ymplayer_map history.txt
@@ -0,0 +1,3 @@
+| Module                          | Partition | Slices        | Slice Reg     | LUTs          | LUTRAM        | BRAM      | MULT18X18 | BUFG  | DCM   | Full Hierarchical Name                                                                                           |
+| +u_jt51 v1.0                    |           | 60/2001       | 62/1197       | 2/2697        | 0/446         | 0/1       | 0/2       | 1/1   | 0/0   | ymplayer/u_jt51                                                                                                  |
+| +u_jt51 v1.1                    |           | 108/2029      | 62/1270       | 52/2504       | 0/439         | 0/1       | 0/2       | 1/1   | 0/0   | ymplayer/u_jt51                                                                                                  |
diff --git a/syn/xilinx/contra_snd/doc/ymplayer_map jt51 v1.0.mrp b/syn/xilinx/contra_snd/doc/ymplayer_map jt51 v1.0.mrp
diff --git a/syn/xilinx/contra_snd/hdl/ymplayer.v b/syn/xilinx/contra_snd/hdl/ymplayer.v
@@ -231,7 +231,8 @@ bus_manager #(RAM_MSB) bus_mng(
 	);
 
 `ifndef NOCPU
-wire cpu_firq_n = 1'b1;
+wire cpu_firq_n = sw_sel[0] ? jt_irq_n : 1'b1;
+
 
 mc6809i cpu_good(
     .D		( cpu_data_in	),

diff --git a/syn/xilinx/contra_snd/runme/ddragon b/syn/xilinx/contra_snd/runme/ddragon
@@ -1,18 +1,21 @@
 #!/bin/bash
-stty 921600 raw -echo
 UART=/dev/ttyUSB0
+stty -F $UART 921600 raw -echo
 echo Volcando...
 cat 21j-0-1 > $UART
-echo Volcado completo
 
-i=1
-while [ $i -lt 31 ]; do
-	x=$(printf "%X" $i)
-	echo Cancion 0x$x
-	echo -e -n "\x$x" > $UART
-	timeout 8m cat $UART > $x.jtx
-	echo -e -n "\x$FF" > $UART
-	i=$((i+1))
-done
+# echo Volcado completo
+
+# i=1
+# while [ $i -lt 31 ]; do
+# 	x=$(printf "%X" $i)
+# 	echo Cancion 0x$x
+# 	echo -e -n "\x$x" > $UART
+# 	timeout 8m cat $UART > $x.jtx
+# 	echo -e -n "\x$FF" > $UART
+# 	i=$((i+1))
+# done
+
+echo -e -n "\x1" > $UART
 
 reset