Merge #66

66: Fix off-by-one for maximum PCLK1 clock rate. r=japaric a=sapir
japaric · Mar 26, 2018 · 9d84254 · 9d84254
2 parents 897596f + 1605174
commit 9d84254
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -175,7 +175,7 @@ impl CFGR {
         let ppre1 = 1 << (ppre1_bits - 0b011);
         let pclk1 = hclk / u32(ppre1);
 
-        assert!(pclk1 < 36_000_000);
+        assert!(pclk1 <= 36_000_000);
 
         let ppre2_bits = self.pclk2
             .map(|pclk2| match hclk / pclk2 {