This patch adds initial J1b support for the ULX3S board, which is based on the
Lattice ECP5 FPGA and can be programmed with either the Trellis (Yosys) or
Diamond (vendor) toolchain.

Currently only the J1b core and UART are hooked up. So no LEDs, GPIO ports,
buttons, SDRAM, etc.. support yet.

You can connect to the core with the `shell.py` script, and you can replicate
the bootstap process: compiling swapforth.fs, writing out a new nuc.hex file
containing the new words and creating a new bitstream containing the new `.hex`
file. Flashing that on the ULX3S seems to replicate a functioning Forth system.

The `bram` and `ram16k` modules were split out from the `xilinx-top.v` file into
`ram.v` to foster some code reuse. Thanks to improved handling of bram within
Yosys, the modules could be reused as is.

Note that the changes weren't tested on either the Diamond or Xilinx
toolchains. The changes to Xilinx parts were minimal so hopefully no regression
was introduced. As for Diamond, it made sense to me to include the
Makefile-related parts needed to compile for Diamond to aid others wanting to
make this work.

Also added to ULX3S readme for memory map layout updates and examples.

The ULX3S has 2x28 IO pins that can be used either individually or as
differential pairs. Currently we're going to assume an individual setup (you can
configure their behaviour in the .lpf file).

The convention is to see them as gp[27] (GPIO positive) and gn[27] (GPIO
negative) arrays; this is how they're numbered on the board itself. Note that
positive and negative moniker are irrelevant in the current configuration as the
ports aren't set up as differential pairs. To work with this convention, we
split out the GPIO address space into 0x00XX and 0x02XX for setting in/output
values of gp and gn pins respectively, and use 0x01XX and 0x3XX for setting the
direction of the gn and gp pins.