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update Verilator-related files to compile on version 4.228 #76

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update Verilator-related files to compile on version 4.228 #76

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Commits on Oct 18, 2022

  1. update Verilator-related files to compile on version 4.228 

    - Starting from Verilator version 4.210, the model class is an interface
object. For reaching Verilog variables internal to a module this means that we
need to include an extra header in cpp files that reference them (#include
"Vj1a___024root.h"). And they're now part of a rootp class which is a member of
the model class; we need to add an extra level of indirection. So
'top->v__DOT__ram_prog[i] = v;' becomes 'top->rootp->v__DOT__ram_prog[i] =
v;'. See https://verilator.org/guide/latest/connecting.html for more words.

- I don't know when these were introduced, but Verilator has become more strict
about allowing assignments to wires. So 'insn' has become a reg as we assign to
it inside a procedural block. And the 'wire uart0_(wr|rd) = ..' wire
declarations on line 60/61 were duplicates of the module port declarations.
    @stuij
    stuij committed Oct 18, 2022
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