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[LLVMGPU] Support i8 MFMA intrinsics in GPUTileAndFuse pipeline #18104

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merged 1 commit into from
Aug 6, 2024

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@Max191 Max191 commented Aug 5, 2024

This PR simply adds MFMA_I8_16x16x32_I32 to the list of allowed enums in MMAAttr::populateOperandOffsetsSizesStrides. This enables the logic to pack and lower a contraction to this intrinsic with the GPUTileAndFuse. The layout for MFMA_I8_16x16x32_I32 is very similar to the layout for MFMA_F16_16x16x16_F32, which is already supported, so the pipeline is already ready to handle the i8 intrinsic case. Numerical correctness has been verified on an MI300 card for a 256x256x256 matmul.

Signed-off-by: Max Dawkins <max.dawkins@gmail.com>
@Max191 Max191 force-pushed the tile-and-fuse-i8-intrinsics branch from d769502 to d074a42 Compare August 5, 2024 19:56
@Max191 Max191 marked this pull request as ready for review August 5, 2024 19:56
@Max191 Max191 requested a review from hanhanW August 5, 2024 19:56
@Max191 Max191 merged commit 1c50edd into iree-org:main Aug 6, 2024
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@Max191 Max191 deleted the tile-and-fuse-i8-intrinsics branch October 25, 2024 14:17
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2 participants