v1.9

Tested mainly with Vivado 2018.3 and 2019.2.

Contains Ethernet-based example designs for:

• Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
• Xilinx KC705 eval board
• Xilinx KCU105 eval board
• Xilinx VCU118 eval board
• Xilinx ZCU102 eval board
• PC053a

And PCIe-based example designs for:

• HiTech Global K800
• Xilinx VCU118 eval board

Bugfixes

• Xilinx example projects: Fix typo ipbb add git URL in README
• Updated dependency files to be compatible with latest tags of IPBB (i.e. dev/2021f) [issue #191]

Minor improvements¶

• ICAP slave: Added description field to address table [issue #180]