Skip to content

Commit

Permalink
Merge pull request #197 from ipbus/feature/rarp-select-port
Browse files Browse the repository at this point in the history
Exposing rarp select ports through infra interfaces
  • Loading branch information
alessandrothea authored Sep 23, 2021
2 parents bb687c4 + 134df68 commit c1017ba
Show file tree
Hide file tree
Showing 8 changed files with 434 additions and 422 deletions.
90 changes: 46 additions & 44 deletions boards/kc705/basex/synth/firmware/hdl/kc705_basex_infra.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -36,29 +36,30 @@ use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;

entity kc705_basex_infra is
generic (
CLK_AUX_FREQ: real := 40.0 -- Default: 40 MHz clock - LHC
);
port(
eth_clk_p: in std_logic; -- 125MHz MGT clock
eth_clk_n: in std_logic;
eth_rx_p: in std_logic; -- Ethernet MGT input
eth_rx_n: in std_logic;
eth_tx_p: out std_logic; -- Ethernet MGT output
eth_tx_n: out std_logic;
sfp_los: in std_logic;
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk_aux_o: out std_logic; -- 40MHz generated clock
rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
generic (
CLK_AUX_FREQ : real := 40.0 -- Default: 40 MHz clock - LHC
);
port(
eth_clk_p : in std_logic; -- 125MHz MGT clock
eth_clk_n : in std_logic;
eth_rx_p : in std_logic; -- Ethernet MGT input
eth_rx_n : in std_logic;
eth_tx_p : out std_logic; -- Ethernet MGT output
eth_tx_n : out std_logic;
sfp_los : in std_logic;
clk_ipb_o : out std_logic; -- IPbus clock
rst_ipb_o : out std_logic;
clk_aux_o : out std_logic; -- 40MHz generated clock
rst_aux_o : out std_logic;
nuke : in std_logic; -- The signal of doom
soft_rst : in std_logic; -- The signal of lesser doom
leds : out std_logic_vector(1 downto 0); -- status LEDs
mac_addr : in std_logic_vector(47 downto 0); -- MAC address
ip_addr : in std_logic_vector(31 downto 0); -- IP address
rarp_select : in std_logic; -- enable RARP
ipb_in : in ipb_rbus; -- ipbus
ipb_out : out ipb_wbus
);

end kc705_basex_infra;

Expand Down Expand Up @@ -142,26 +143,27 @@ begin

-- ipbus control logic

ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
ipbus : entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
RARP_select => rarp_select,
pkt => pkt
);

end rtl;
55 changes: 28 additions & 27 deletions boards/kc705/basex/synth/firmware/hdl/top_kc705_basex.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -64,33 +64,34 @@ begin

-- Infrastructure

infra: entity work.kc705_basex_infra
port map(
eth_clk_p => eth_clk_p,
eth_clk_n => eth_clk_n,
eth_tx_p => eth_tx_p,
eth_tx_n => eth_tx_n,
eth_rx_p => eth_rx_p,
eth_rx_n => eth_rx_n,
sfp_los => sfp_los,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
clk_aux_o => clk_aux,
rst_aux_o => rst_aux,
nuke => nuke,
soft_rst => soft_rst,
leds => leds(1 downto 0),
mac_addr => mac_addr,
ip_addr => ip_addr,
ipb_in => ipb_in,
ipb_out => ipb_out
);

leds(3 downto 2) <= '0' & userled;
sfp_tx_disable <= '0';

mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
infra : entity work.kc705_basex_infra
port map(
eth_clk_p => eth_clk_p,
eth_clk_n => eth_clk_n,
eth_tx_p => eth_tx_p,
eth_tx_n => eth_tx_n,
eth_rx_p => eth_rx_p,
eth_rx_n => eth_rx_n,
sfp_los => sfp_los,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
clk_aux_o => clk_aux,
rst_aux_o => rst_aux,
nuke => nuke,
soft_rst => soft_rst,
leds => leds(1 downto 0),
mac_addr => mac_addr,
ip_addr => ip_addr,
rarp_select => '0',
ipb_in => ipb_in,
ipb_out => ipb_out
);

leds(3 downto 2) <= '0' & userled;
sfp_tx_disable <= '0';

mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n

-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
Expand Down
Loading

0 comments on commit c1017ba

Please sign in to comment.