[SYCL] Always pass -target option to clang-offload-wrapper

SYCL Runtime will need to know the target information for each image so
that the images can be properly dispatched between correspondent devices

Signed-off-by: Sergey Semenov <sergey.semenov@intel.com>
Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>

clang/lib/Driver/ToolChains/Clang.cpp

@@ -6737,23 +6737,24 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,
   SmallString<128> HostTripleOpt("-host=");
   HostTripleOpt += getToolChain().getAuxTriple()->str();
   WrapperArgs.push_back(C.getArgs().MakeArgString(HostTripleOpt));
+
+  llvm::Triple TT = getToolChain().getTriple();
+  SmallString<128> TargetTripleOpt = TT.getArchName();
   // When wrapping an FPGA device binary, we need to be sure to apply the
   // appropriate triple that corresponds (fpga_aoc[xr]-intel-<os>-sycldevice)
   // to the target triple setting.
-  if (getToolChain().getTriple().getSubArch() ==
-          llvm::Triple::SPIRSubArch_fpga &&
+  if (TT.getSubArch() == llvm::Triple::SPIRSubArch_fpga &&
       TCArgs.hasArg(options::OPT_fsycl_link_EQ)) {
-    llvm::Triple TT;
     auto *A = C.getInputArgs().getLastArg(options::OPT_fsycl_link_EQ);
     TT.setArchName((A->getValue() == StringRef("early")) ? "fpga_aocr"
                                                          : "fpga_aocx");
     TT.setVendorName("intel");
     TT.setOS(llvm::Triple(llvm::sys::getProcessTriple()).getOS());
     TT.setEnvironment(llvm::Triple::SYCLDevice);
-    SmallString<128> TargetTripleOpt("-target=");
-    TargetTripleOpt += TT.str();
-    WrapperArgs.push_back(C.getArgs().MakeArgString(TargetTripleOpt));
+    TargetTripleOpt = TT.str();
   }
+  WrapperArgs.push_back(
+      C.getArgs().MakeArgString(Twine("-target=") + TargetTripleOpt));
 
   // TODO forcing offload kind is a simplification which assumes wrapper used
   // only with SYCL. Device binary format (-format=xxx) option should also come

clang/test/Driver/sycl-offload-intelfpga.cpp

@@ -63,7 +63,7 @@
 // CHK-FPGA: llvm-no-spir-kernel{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT3:.+\.o]]"
 // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT3]]" "-o" "[[OUTPUT4:.+\.bc]]"
 // CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "[[OUTPUT4]]"
-// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT6:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-kind=sycl" "[[OUTPUT5]]"
+// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT6:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "[[OUTPUT5]]"
 // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[OUTPUT6]]"
 // CHK-FPGA: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" {{.*}} "-outputs=[[FINALLINK4:.+\.txt]]" "-unbundle"
 // CHK-FPGA: {{link|ld}}{{.*}} "@[[FINALLINK4]]" "[[FINALLINK2]]" "[[FINALLINK]]" "[[FINALLINK3]]"

clang/test/Driver/sycl-offload.c

@@ -504,7 +504,9 @@
 // CHK-TOOLS-FPGA: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]"
 // CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]"
 // CHK-TOOLS-CPU: ioc{{.*}} "-ir=[[OUTPUT4:.+\.out]]" {{.*}} "-binary=[[OUTPUT3]]"
-// CHK-TOOLS-AOT: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-kind=sycl" "[[OUTPUT4]]"
+// CHK-TOOLS-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga{{.*}}" "-kind=sycl" "[[OUTPUT4]]"
+// CHK-TOOLS-GEN: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_gen{{.*}}" "-kind=sycl" "[[OUTPUT4]]"
+// CHK-TOOLS-CPU: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_x86_64{{.*}}" "-kind=sycl" "[[OUTPUT4]]"
 // CHK-TOOLS-AOT: llc{{.*}} "-filetype=obj" "-o" "[[OUTPUT6:.+\.o]]" "[[OUTPUT5]]"
 // CHK-TOOLS-FPGA: clang{{.*}} "-triple" "spir64_fpga-unknown-{{.*}}-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
 // CHK-TOOLS-GEN: clang{{.*}} "-triple" "spir64_gen-unknown-linux-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"