EDAC/ieh: Add I/O device EDAC driver for Intel CPUs with IEH

Integrated Error Handlers (IEHs) are PCIe devices which aggregate and report error events of different severities (correctable, non-fatal uncorrectable, and fatal uncorrectable) from various I/O devices, e.g., PCIe devices, legacy PCI devices. Each error severity is notified by one of {SMI, NMI, MCE} which is configured by BIOS/platform firmware. The first IEH-supported platform is Intel Tiger Lake-U CPU. The driver reads/prints the error severity and error source (bus/device/function) logged in the IEH(s) and restarts the system on fatal I/O device error. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
intel · Dec 15, 2023 · 9f721ed · 9f721ed
1 parent 1afcf24
commit 9f721ed
Show file tree

Hide file tree

Showing 3 changed files with 795 additions and 0 deletions.
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
@@ -281,6 +281,16 @@ config EDAC_IGEN6
 	  This In-Band ECC is first used on the Elkhart Lake SoC but
 	  may appear on others in the future.
 
+config EDAC_IEH
+	tristate "Intel Integrated Error Handler"
+	depends on PCI && X86_64
+	help
+	  Support for error detection and correction on the Intel
+	  CPU using I/O IEH (Integrated Error Handler). IEHs are PCIe
+	  devices which aggregate and report error events of different
+	  severities from various I/O devices, e.g., PCIe devices and
+	  legacy PCI devices.
+
 config EDAC_MPC85XX
 	bool "Freescale MPC83xx / MPC85xx"
 	depends on FSL_SOC && EDAC=y

diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_EDAC_I7CORE)		+= i7core_edac.o
 obj-$(CONFIG_EDAC_SBRIDGE)		+= sb_edac.o
 obj-$(CONFIG_EDAC_PND2)			+= pnd2_edac.o
 obj-$(CONFIG_EDAC_IGEN6)			+= igen6_edac.o
+obj-$(CONFIG_EDAC_IEH)			+= ieh_edac.o
 obj-$(CONFIG_EDAC_E7XXX)		+= e7xxx_edac.o
 obj-$(CONFIG_EDAC_E752X)		+= e752x_edac.o
 obj-$(CONFIG_EDAC_I82443BXGX)		+= i82443bxgx_edac.o