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RT118x clock initialization #185

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merged 3 commits into from
Jan 15, 2025
Merged

RT118x clock initialization #185

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32c1788
Clock configuration for RT118x
glaeqen Dec 20, 2024
be4d19e
Add clock init call to the bsp
glaeqen Dec 20, 2024
c994564
Remove hard-dependency on `defmt`
glaeqen Jan 13, 2025
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4 changes: 3 additions & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ license = { workspace = true }
edition = { workspace = true }
version = "0.6.0"

[dependencies.cortex-m]
version = "0.7"

[dependencies.cfg-if]
version = "1.0"

Expand Down Expand Up @@ -154,7 +157,6 @@ codegen-units = 256
######################################

[dev-dependencies]
cortex-m = "0.7"
imxrt-rt = { workspace = true }
menu = "0.3.2"
rtic = { version = "2.0", features = ["thumbv7-backend"] }
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29 changes: 24 additions & 5 deletions board/src/imxrt1180evk-cm33.rs
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Expand Up @@ -29,12 +29,31 @@ pub struct Specifics {

impl Specifics {
pub(crate) fn new(_: &mut crate::Common) -> Self {
let iomuxc = unsafe { ral::iomuxc::IOMUXC::instance() };
let iomuxc_aon = unsafe { ral::iomuxc_aon::IOMUXC_AON::instance() };
let pads = imxrt_hal::iomuxc::into_pads(iomuxc, iomuxc_aon);
let ral::Instances {
IOMUXC,
IOMUXC_AON,
RGPIO4,
mut ANADIG_OSC,
mut ANADIG_PLL,
mut ANADIG_PMU,
mut CCM,
mut DCDC,
mut PHY_LDO,
..
} = unsafe { ral::Instances::instances() };

let gpio4 = unsafe { ral::rgpio::RGPIO4::instance() };
let mut gpio4 = imxrt_hal::rgpio::Port::new(gpio4);
imxrt_hal::ccm::init(
&mut ANADIG_OSC,
&mut ANADIG_PLL,
&mut ANADIG_PMU,
&mut CCM,
&mut DCDC,
&mut PHY_LDO,
);
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The table shows my root clock measurements after this call returns. I took these measurements using the debugger. These frequencies LGTM.

                          Name | Current (Hz) |     Min (Hz) |     Max (Hz) | Max-Min (Hz)
------------------------------------------------------------------------------------------
             FLEXSPI1_CLK_ROOT |    132934656 |    132934656 |    132935168 |          512
                  M33_CLK_ROOT |    240020992 |    240020992 |    240021504 |          512
                   OSC_24M_OUT |     24002048 |     24002048 |     24002048 |            0
                    OSC_RC_24M |     24113152 |     24112640 |     24114176 |         1536
                   OSC_RC_400M |    399403008 |    399403008 |    399549952 |       146944
                  PLL_480_DIV2 |    240020480 |    240020480 |    240021504 |         1024
                   PLL_480_OUT |    480041984 |    480040960 |    480043008 |         2048
                  PLL_480_PFD0 |    664673792 |    664672768 |    664675328 |         2560
                  PLL_480_PFD1 |            0 |          ??? |            0 |          ???
                  PLL_480_PFD2 |            0 |          ??? |            0 |          ???
                  PLL_480_PFD3 |            0 |          ??? |            0 |          ???

Here is the tool for folks who want to reproduce this test.

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Pretty nice, that means that my diag module is kind of redundant. It should be at least hidden behind a defmt feature flag because as of now it's useless without it anyway.

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I noticed that with changes from cd76df105fe0f1056efca8f37b89ef2485515222 my diag module stopped working after the write to TRDC1.MDA_W0_2_DFMT1 (thus TODO comment). Did not investigate further but probably I violate some invariants.

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Just curious: Does stop working mean that the TRDC blocked the CPU's access to the CCM observation registers? Or, were the CCM observation measurements erroneous after writing to TRDC1.MDA_W0_2_DFMT1?

Manipulating TRDC1.MDA_W0_2_DFMT1 doesn't seem to affect the debugger's access to the CCM's observation registers. I merged cd76df105 into this branch, generating mciantyre@b3b004e. Examples still worked, and I could still generate that table from above.


let pads = imxrt_hal::iomuxc::into_pads(IOMUXC, IOMUXC_AON);

let mut gpio4 = imxrt_hal::rgpio::Port::new(RGPIO4);
let led = gpio4.output(pads.gpio_ad.p27);

Specifics { led }
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