Setup for TDC v2 based on ring

README.md

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 ## Copyright 2024 by Harald Pretl, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria
 
-A TDC is implemented in Verilog and synthesized, with a configurable delay length, and based on an interleaved inverter chain.
+A TDC is implemented in Verilog and synthesized, with a configurable delay length, and based on an interleaved inverter ring.
 
 The result of the delay line capture is output directly, without any bubble correction or coding.
 

docs/info.md

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 ## How it works
 
-This is a simple synthesized time-to-digital converter (TDC), consisting of a delay line and parallel capture FF. Depending on `__TDC_INTERLEAVED__` either a simple or an interleaved delay line is implemented.
-
-In the TT 1x1 block size a 192-stage interleaved delay can be fitted.
+This is a simple synthesized time-to-digital converter (TDC), consisting of a delay line ring and parallel capture FF. Depending on `__TDC_INTERLEAVED__` either a simple or an interleaved delay line is implemented.
 
 ## How to test