update examples

examples/advanced/axi-stream.wal

@@ -1,5 +1,5 @@
 ;; This examples analyzes the uart->axi converter from https://github.com/fcayci/vhdl-axis-uart.
-(load "uart-axi.fst" t)
+(load "uart-axi.fst")
 
 (alias clk uut_rx.clk)
 (alias ready uut_rx.m_axis_tready)

examples/advanced/axi-stream.wawk

@@ -37,8 +37,8 @@ clk, valid, ready: {
     if (ack_delay == 0) {
         print("[OK]");
     } else {
-	printf("[DELAY %d]\n", ack_delay);
-    };
+        printf("[DELAY %d]\n", ack_delay);
+    }
 }
 
 // executed whenever the data changes whithout being acknowledged
@@ -51,7 +51,7 @@ clk, (data != data@2), valid, !ready: {
 END: {
     if (bytes_dropped) {
       printf("\nWARNING: %d bytes dropped due to an unavailable AXI sink!\n", bytes_dropped);
-    };
+    }
 
     printf("Average delay until byte acknowlede %d cycles\n", average(byte_delay));
 }

examples/advanced/repl.wal

@@ -2,7 +2,7 @@
 ;; when an error is detected. This allows to inspect signal
 ;; values in the context in which the error occurred.
 
-(load "../basics/counter.fst" t)
+(load "../basics/counter.fst")
 
 ;; check if the tb.overflow signal is set to high whenever the counter overflows
 ;; if tb.overflow is not high when the counter overflows drop into a REPL

examples/basics/basics1.wal

@@ -3,7 +3,7 @@
 ;; To get access to the waveform in "counter.vcd" first we must load it.
 ;; The "load" function loads the waveform from the file pointed to by the first
 ;; parameter and registers it using the name passed as the second parameter.
-(load "counter.fst" t)
+(load "counter.fst")
 
 ;; Now we can print all signal names that are in the waveform.
 ;; "SIGNALS" is a special variable containing a list of all signal names.

examples/basics/basics2.wal

@@ -4,7 +4,7 @@
 ;; Our goal in this example is to find all the time indices at which the
 ;; counter overflows.
 
-(load "counter.fst" t)
+(load "counter.fst")
 
 ;; We have to check on each time index if the counter is overflowing and if
 ;; it is we want to print the time index.

examples/print-vcd/print-vcd.wal

@@ -15,7 +15,7 @@
       (print "usage: print-vcd filename scope")
       (exit 1))
 
-(load args[0] t)
+(load args[0])
 
 ;; get longest signal name
 (define max-signal (max (map (fn [x] (length x)) SIGNALS)))
@@ -59,7 +59,9 @@
 		    [n (get signal)@1])
 		(cond [(= v 0) (printf "────")]
 	      	      [(= v "x") (printf "XXXX")]
-		      [(!= p v) (printf "┤%3x" v)]
+		      [(!= p v) (if (int? v)
+                        (printf "┤%3x" v)
+                        (printf "┤%3s" v))]
 		      [(&& (!= p v) (!= v n)) (printf "┤%2x├" v)]
 		      [(!= v n) (printf "   ├")]
 	      	      [#t (printf "    ")]))
@@ -81,5 +83,5 @@
 
 ;; Set current scope
 (if (> (length args) 1)
-    (in-scope args[1] (render SIGNALS))
+    (in-scope args[1] (render LOCAL-SIGNALS))
     (render SIGNALS))

examples/riscv-profile/profile.py

@@ -53,7 +53,7 @@ def ranges(binary_file):
 
     wal = Wal()
     wal.load(VCD)
-    wal.eval_str('(require config)') # require config script to get concrete signal names
+    wal.eval_str('(eval-file config)') # require config script to get concrete signal names
     wal.eval_str('''(defun count-function [addr]
                   (for [f funcs]
                     (when (&& (>= addr f[1]) (<= addr f[2]))

examples/virtual-examples/virtual1.wal

@@ -1,7 +1,7 @@
 ;; In this example we are adding some virtual signals to the counter trace.
 ;; Inspired by https://www.tessla.io/intro/
 
-(load "../basics/counter.fst" t)
+(load "../basics/counter.fst")
 
 ;; indicates when the temperature is dangerously low
 (defsig low (< tb.dut.counter 3))

examples/virtual-examples/virtual2.wal

@@ -1,6 +1,6 @@
 ;; In this example we count how long the reset is high
 
-(load "../basics/counter.fst" t)
+(load "../basics/counter.fst")
 
 (defsig count-reset (if tb.dut.reset (+ count-reset@-1 tb.dut.reset) 0))
 

examples/virtual-examples/virtual3.wal

@@ -1,4 +1,4 @@
-(load "../basics/counter.fst" t)
+(load "../basics/counter.fst")
 
 (defsig last-overflow (if (&& tb.dut.overflow (! tb.dut.overflow@-1)) INDEX last-overflow@-1))
 (defsig diff (if (!= last-overflow@-1 last-overflow) (- last-overflow last-overflow@-1) 0))

examples/virtual-examples/vtrace.wal

@@ -8,7 +8,7 @@
 (defsig overflow (if (= cnt 3) 1 0))                  
 
 ;; render the virtual trace
-(require print-vcd)
+(eval-file print-vcd)
 (render '("clk" "cnt" "overflow"))
 
 ;; dump the trace to "t.vcd", experimental

examples/wawk/vexriscv-pipeline/.gitignore

@@ -0,0 +1 @@
+index.html

wal/implementation/virtual.py

@@ -39,7 +39,7 @@ def op_new_trace(seval, args):
     assert isinstance(args[0], Symbol), 'new-trace: first argument must be a symbol'
     assert isinstance(args[1], int), 'new-trace: second argument must be an int'
 
-    seval.traces.traces[args[0].name] = TraceVirtual(args[0].name, args[1])
+    seval.traces.traces[args[0].name] = TraceVirtual(args[0].name, args[1], seval.traces)
     seval.traces.n_traces += 1
 
 

wal/trace/virtual.py

@@ -5,8 +5,8 @@
 class TraceVirtual(Trace):
     '''Holds data for one virtual trace.'''
 
-    def __init__(self, tid, max_index):
-        super().__init__(tid, 'virtual')
+    def __init__(self, tid, max_index, container):
+        super().__init__(tid, 'virtual', container)
         self.signals = set()
         self.rawsignals = self.signals
         self.max_index = max_index
@@ -19,8 +19,11 @@ def dump_vcd(self):
         with open(self.tid + '.vcd', 'w', encoding='utf-8') as f:
             f.write('$version\n    WAL\n$end\n')
             f.write('$timescale\n    1ps\n$end\n')
+            f.write(f'$scope module {self.tid} $end\n')
             for signal in self.signals:
                 f.write(f'$var reg 32 {signal} {signal} [31:0] $end\n')
+
+            f.write('$upscope $end\n')
             f.write('$enddefinitions $end\n')
 
             old_index = self.index