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Enabling CI for AMD with new runner.. #2034

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Enabling CI for AMD with new runner.. #2034

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Narsil
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@Narsil Narsil commented Jun 6, 2024

What does this PR do?

Uses new runner for AMD ci.

Fixes # (issue)

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  • This PR fixes a typo or improves the docs (you can dismiss the other checks if that's the case).
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  • Did you write any new necessary tests?

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@Narsil Narsil mentioned this pull request Jun 6, 2024
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@Narsil Narsil requested review from OlivierDehaene and danieldk and removed request for OlivierDehaene June 9, 2024 20:39
@@ -106,7 +106,7 @@ def _load_qkv(config, prefix: str, weights, head_size, num_heads):
for i in range(3):
tensor = slice_[:, start + i * single_size : stop + i * single_size]
tensors.append(tensor)
weight = torch.cat(tensors, dim=1).T
weight = torch.cat(tensors, dim=1).T.contiguous()
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These non-contiguous weights were causing wrong generation on ROCm with LLMM1 that has no check on input tensors contiguity.

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Narsil commented Jun 25, 2024

Super seeded by #2109

@Narsil Narsil closed this Jun 25, 2024
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2 participants