feat(verilog): add verible (#22481)

.editorconfig

@@ -102,6 +102,10 @@ indent_style = space
 indent_size = 2
 indent_style = space
 
+[*.v]
+indent_size = 2
+indent_style = space
+
 [*.vhd]
 indent_size = 2
 indent_style = space

.github/workflows/.lint.yml

@@ -32,6 +32,7 @@ jobs:
       sql: ${{ steps.filter.outputs.sql }}
       terraform: ${{ steps.filter.outputs.terraform }}
       toml: ${{ steps.filter.outputs.toml }}
+      verilog: ${{ steps.filter.outputs.verilog }}
       vhdl: ${{ steps.filter.outputs.vhdl }}
       xml: ${{ steps.filter.outputs.xml }}
       yaml: ${{ steps.filter.outputs.yaml }}
@@ -219,6 +220,11 @@ jobs:
               - '.github/workflows/.lint.yml'
               - 'taplo.toml'
               - '**/*.toml'
+            verilog:
+              - '.github/workflows/.lint.yml'
+              - 'pyproject.toml'
+              - 'uv.lock'
+              - '**/*.v'
             vhdl:
               - '.github/workflows/.lint.yml'
               - 'pyproject.toml'
@@ -1436,6 +1442,34 @@ jobs:
             fmt \
               --check
 
+  lint-verilog:
+    name: Verilog
+    needs: detect-changes
+    if: ${{ needs.detect-changes.outputs.verilog == 'true' }}
+    runs-on: ubuntu-24.04
+    environment: test
+    timeout-minutes: 10
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4.2.2
+      - name: Lint Verilog
+        run: |
+          git ls-files "**/*.v" | \
+            xargs docker run \
+              --rm \
+              --volume="$(pwd):/workspace" \
+              --workdir=/workspace \
+              hdlc/verible:latest \
+              verible-verilog-lint
+          git ls-files "**/*.v" | \
+            xargs docker run \
+              --rm \
+              --volume="$(pwd):/workspace" \
+              --workdir=/workspace \
+              hdlc/verible:latest \
+              verible-verilog-format \
+                --verify
+
   lint-vhdl:
     name: VHDL
     needs: detect-changes

.mergify.yml

@@ -137,6 +137,9 @@ pull_request_rules:
       - or:
           - check-success=Lint / XML
           - check-skipped=Lint / XML
+      - or:
+          - check-success=Lint / Verilog
+          - check-skipped=Lint / Verilog
       - or:
           - check-success=Lint / VHDL
           - check-skipped=Lint / VHDL

Makefile

@@ -308,6 +308,10 @@ lint-toml:
 	taplo fmt --check
 lint-toml-fix:
 	taplo fmt
+lint-verilog:
+	verible-verilog-lint $$(git ls-files "**/*.v") && verible-verilog-format --verify $$(git ls-files "**/*.v")
+lint-verilog-fix:
+	verible-verilog-lint --autofix=inplace $$(git ls-files "**/*.v") && verible-verilog-format --inplace $$(git ls-files "**/*.v")
 lint-vhdl:
 	uv run poe lint-vhdl
 lint-vhdl-fix:

README.md

@@ -699,6 +699,7 @@ The diagram illustrates the repository's architecture, which is considered overl
 - **Taplo** - TOML code formatter
 - **terraform** - Terraform code formatter
 - **tsc** - TypeScript static type checker
+- **Verible** - Verilog code formatter and linter
 - **VHDL Style Guide (VSG)** - VHDL code formatter
 - **@prettier/plugin-xml** - XML formatter
 - **yamllint** - YAML linter

digital-design/verilog/src/main.v

@@ -1,69 +1,65 @@
 module counter_4bit (
-    input wire clk,         // Clock input
-    input wire rst,         // Reset input
-    output reg [3:0] count  // 4-bit counter output
+    input  wire       clk,   // Clock input
+    input  wire       rst,   // Reset input
+    output reg  [3:0] count  // 4-bit counter output
 );
 
-    // Sequential logic block
-    always @(posedge clk) begin
-        if (rst) begin
-            // Synchronous reset
-            count <= 4'b0000;
-        end
-        else begin
-            // Increment counter
-            count <= count + 1;
-        end
+  // Sequential logic block
+  always @(posedge clk) begin
+    if (rst) begin
+      // Synchronous reset
+      count <= 4'b0000;
+    end else begin
+      // Increment counter
+      count <= count + 1;
     end
-
+  end
 endmodule
 
-// Testbench
-module counter_4bit_tb;
-
-    // Testbench signals
-    reg clk;
-    reg rst;
-    wire [3:0] count;
-
-    // Instantiate the counter
-    counter_4bit counter_inst (
-        .clk(clk),
-        .rst(rst),
-        .count(count)
-    );
+// Test bench
+module main;
+  // Test bench signals
+  reg clk;
+  reg rst;
+  wire [3:0] count;
 
-    // Clock generation
-    initial begin
-        clk = 0;
-        forever #5 clk = ~clk;
-    end
+  // Instantiate the counter
+  counter_4bit counter_inst (
+      .clk  (clk),
+      .rst  (rst),
+      .count(count)
+  );
 
-    // Test stimulus
-    initial begin
-        // Initialize
-        rst = 1;
+  // Clock generation
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
 
-        // Wait for 2 clock cycles
-        #20;
+  // Test stimulus
+  initial begin
+    // Initialize
+    rst = 1;
 
-        // Release reset
-        rst = 0;
+    // Wait for 2 clock cycles
+    #20;
 
-        // Let it count for a while
-        #160;
+    // Release reset
+    rst = 0;
 
-        // Apply reset again
-        rst = 1;
-        #20;
+    // Let it count for a while
+    #160;
 
-        // End simulation
-        $finish;
-    end
+    // Apply reset again
+    rst = 1;
+    #20;
 
-    // Monitor changes
-    initial begin
-        $monitor("Time=%0t rst=%b count=%b", $time, rst, count);
-    end
+    // End simulation
+    $finish;
+  end
 
+  // Monitor changes
+  initial begin
+    $monitor("Time=%0t rst=%b count=%b", $time, rst, count);
+  end
 endmodule

pyproject.toml

@@ -33,8 +33,8 @@ lint-c-cpp-cpplint = "cpplint"
 lint-cmake = { shell = "cmakelint $(git ls-files '**/CMakeLists.txt')" }
 lint-matlab = { shell = "mh_style $(git ls-files '**/*.m')" }
 lint-matlab-fix = { shell = "mh_style --fix $(git ls-files '**/*.m')" }
-lint-python = { shell = "ruff format --check && ruff check" }
-lint-python-fix = { shell = "ruff format && ruff check --fix --unsafe-fixes" }
+lint-python = { shell = "ruff check && ruff format --check" }
+lint-python-fix = { shell = "ruff check --fix --unsafe-fixes && ruff format" }
 lint-sql = "sqlfluff lint"
 lint-sql-fix = "sqlfluff fix --force"
 lint-vhdl = { shell = "vsg --filename $(git ls-files '**/*.vhd')" }