RFC: add draft to support WebAssembly within the kernel

Cargo.toml

@@ -72,6 +72,7 @@ semihosting = ["dep:semihosting"]
 shell = ["simple-shell"]
 idle-poll = []
 mmap = []
+wasm = ["wasmtime"]
 
 [dependencies]
 hermit-macro = { path = "hermit-macro" }
@@ -110,6 +111,7 @@ talc = { version = "4" }
 time = { version = "0.3", default-features = false }
 volatile = "0.6"
 zerocopy = { version = "0.7", default-features = false }
+wasmtime = { version = "24.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }
 
 [dependencies.smoltcp]
 version = "0.11"

src/arch/aarch64/kernel/longjmp.s

@@ -0,0 +1,18 @@
+# The code is derived from the musl implementation
+# of longjmp.
+.section .text
+.global longjmp
+longjmp:
+	# IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
+	ldp x19, x20, [x0,#0]
+	ldp x21, x22, [x0,#16]
+	ldp x23, x24, [x0,#32]
+	ldp x25, x26, [x0,#48]
+	ldp x27, x28, [x0,#64]
+	ldp x29, x30, [x0,#80]
+	ldr x2, [x0,#104]
+	mov sp, x2
+
+	cmp w1, 0
+	csinc w0, w1, wzr, ne
+	br x30

src/arch/aarch64/kernel/mod.rs

@@ -23,6 +23,9 @@ use crate::arch::aarch64::kernel::serial::SerialPort;
 use crate::arch::aarch64::mm::{PhysAddr, VirtAddr};
 use crate::env;
 
+global_asm!(include_str!("setjmp.s"));
+global_asm!(include_str!("longjmp.s"));
+
 const SERIAL_PORT_BAUDRATE: u32 = 115200;
 
 static mut COM1: SerialPort = SerialPort::new(0x800);

src/arch/aarch64/kernel/setjmp.s

@@ -0,0 +1,16 @@
+# The code is derived from the musl implementation
+# of setjmp.
+.section .text
+.global setjmp
+setjmp:
+    # IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
+	stp x19, x20, [x0,#0]
+	stp x21, x22, [x0,#16]
+	stp x23, x24, [x0,#32]
+	stp x25, x26, [x0,#48]
+	stp x27, x28, [x0,#64]
+	stp x29, x30, [x0,#80]
+	mov x2, sp
+	str x2, [x0,#104]
+	mov x0, #0
+	ret

src/arch/riscv64/kernel/longjmp.s

@@ -0,0 +1,23 @@
+# The code is derived from the musl implementation
+# of longjmp.
+.section .text
+.global longjmp
+longjmp:
+    ld s0,    0(a0)
+	ld s1,    8(a0)
+	ld s2,    16(a0)
+	ld s3,    24(a0)
+	ld s4,    32(a0)
+	ld s5,    40(a0)
+	ld s6,    48(a0)
+	ld s7,    56(a0)
+	ld s8,    64(a0)
+	ld s9,    72(a0)
+	ld s10,   80(a0)
+	ld s11,   88(a0)
+	ld sp,    96(a0)
+	ld ra,    104(a0)
+
+	seqz a0, a1
+	add a0, a0, a1
+	ret

src/arch/riscv64/kernel/mod.rs

@@ -12,6 +12,7 @@ pub mod switch;
 pub mod systemtime;
 
 use alloc::vec::Vec;
+use core::arch::global_asm;
 use core::ptr;
 use core::sync::atomic::{AtomicPtr, AtomicU32, AtomicU64, Ordering};
 
@@ -27,6 +28,9 @@ use crate::arch::riscv64::mm::{physicalmem, PhysAddr, VirtAddr};
 use crate::config::KERNEL_STACK_SIZE;
 use crate::env;
 
+global_asm!(include_str!("setjmp.s"));
+global_asm!(include_str!("longjmp.s"));
+
 // Used to store information about available harts. The index of the hart in the vector
 // represents its CpuId and does not need to match its hart_id
 pub static mut HARTS_AVAILABLE: Vec<usize> = Vec::new();

src/arch/riscv64/kernel/setjmp.s

@@ -0,0 +1,22 @@
+# The code is derived from the musl implementation
+# of setjmp.
+.section .text
+.global setjmp
+setjmp:
+	sd s0,    0(a0)
+	sd s1,    8(a0)
+	sd s2,    16(a0)
+	sd s3,    24(a0)
+	sd s4,    32(a0)
+	sd s5,    40(a0)
+	sd s6,    48(a0)
+	sd s7,    56(a0)
+	sd s8,    64(a0)
+	sd s9,    72(a0)
+	sd s10,   80(a0)
+	sd s11,   88(a0)
+	sd sp,    96(a0)
+	sd ra,    104(a0)
+
+	li a0, 0
+	ret

src/arch/x86_64/kernel/longjmp.s

@@ -0,0 +1,19 @@
+# The code is derived from the musl implementation
+# of longjmp.
+#
+# Copyright 2011-2012 Nicholas J. Kain,
+# licensed under standard MIT license
+.section .text
+.global longjmp
+longjmp:
+	xor eax,eax
+	cmp esi, 1              /* CF = val ? 0 : 1 */
+	adc eax, esi            /* eax = val + !val */
+	mov rbx, [rdi]
+	mov rbp, [rdi+8] 
+	mov r12, [rdi+16] 
+	mov r13, [rdi+24] 
+	mov r14, [rdi+32] 
+	mov r15, [rdi+40] 
+	mov rsp, [rdi+48] 
+	jmp [rdi+56]

src/arch/x86_64/kernel/mod.rs

@@ -1,5 +1,6 @@
 #[cfg(feature = "common-os")]
 use core::arch::asm;
+use core::arch::global_asm;
 use core::num::NonZeroU64;
 use core::ptr;
 use core::sync::atomic::{AtomicPtr, AtomicU32, Ordering};
@@ -38,6 +39,9 @@ pub(crate) mod systemtime;
 #[cfg(feature = "vga")]
 mod vga;
 
+global_asm!(include_str!("setjmp.s"));
+global_asm!(include_str!("longjmp.s"));
+
 /// Kernel header to announce machine features
 #[cfg_attr(target_os = "none", link_section = ".data")]
 static mut RAW_BOOT_INFO: Option<&'static RawBootInfo> = None;

src/arch/x86_64/kernel/setjmp.s

@@ -0,0 +1,20 @@
+# The code is derived from the musl implementation
+# of setjmp.
+#
+# Copyright 2011-2012 Nicholas J. Kain,
+# licensed under standard MIT license
+.section .text
+.global setjmp
+setjmp:
+mov [rdi], rbx
+mov [rdi+8], rbp
+mov [rdi+16], r12
+mov [rdi+24], r13
+mov [rdi+32], r14
+mov [rdi+40], r15
+lea rdx, [rsp+8] # rsp without current ret addr
+mov [rdi+48], rdx
+mov rdi, rsp     # save return addr ptr for new rip
+mov [rdi+56], rdx
+xor rax, rax
+ret

src/lib.rs

@@ -94,6 +94,8 @@ mod shell;
 mod synch;
 pub mod syscalls;
 pub mod time;
+#[cfg(feature = "wasm")]
+mod wasm;
 
 #[cfg(target_os = "none")]
 hermit_entry::define_entry_version!();
@@ -157,6 +159,11 @@ extern "C" fn initd(_arg: usize) {
 	#[cfg(not(test))]
 	let (argc, argv, environ) = syscalls::get_application_parameters();
 
+	#[cfg(all(any(target_arch = "x86_64", target_arch = "aarch64"), feature = "wasm"))]
+	if crate::wasm::init().is_err() {
+		error!("Unable to initialized wasm support")
+	}
+
 	// give the IP thread time to initialize the network interface
 	core_scheduler().reschedule();