Skip to content

Commit

Permalink
drm/i915/tgl: Fix Media power gate sequence.
Browse files Browse the repository at this point in the history 
Some media power gates are disabled by default. commit 5d86923
("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
tried to enable it, but it duplicated an existent register.
So, the main PG setup sequences ended up overwriting it.

So, let's now merge this to the main PG setup sequence.

v2: (Chris): s/BIT/REG_BIT, remove useless comment,
    	     remove useless =0, use the right gt,
	     remove rc6 sequence doubt from commit message.

Fixes: 5d86923 ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org#v5.5+
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201111072859.1186070-1-rodrigo.vivi@intel.com
  • Loading branch information
@rodrigovivi @ickle
rodrigovivi authored and ickle committed Nov 11, 2020
1 parent 330b7d3 commit 695dc55
Show file tree
Hide file tree
Showing 3 changed files with 22 additions and 25 deletions.
22 changes: 17 additions & 5 deletions drivers/gpu/drm/i915/gt/intel_rc6.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,9 +56,12 @@ static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)

static void gen11_rc6_enable(struct intel_rc6 *rc6)
{
struct intel_uncore *uncore = rc6_to_uncore(rc6);
struct intel_gt *gt = rc6_to_gt(rc6);
struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
u32 pg_enable;
int i;

/* 2b: Program RC6 thresholds.*/
set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
Expand Down Expand Up @@ -102,10 +105,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);

set(uncore, GEN9_PG_ENABLE,
GEN9_RENDER_PG_ENABLE |
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE);
pg_enable =
GEN9_RENDER_PG_ENABLE |
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;

if (INTEL_GEN(gt->i915) >= 12) {
for (i = 0; i < I915_MAX_VCS; i++)
if (HAS_ENGINE(gt, _VCS(i)))
pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
VDN_MFX_POWERGATE_ENABLE(i));
}

set(uncore, GEN9_PG_ENABLE, pg_enable);
}

static void gen9_rc6_enable(struct intel_rc6 *rc6)
Expand Down
12 changes: 5 additions & 7 deletions drivers/gpu/drm/i915/i915_reg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8984,10 +8984,6 @@ enum {
#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)

#define POWERGATE_ENABLE _MMIO(0xa210)
#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)

#define GTFIFODBG _MMIO(0x120000)
#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
Expand Down Expand Up @@ -9127,9 +9123,11 @@ enum {
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
#define GEN9_PG_ENABLE _MMIO(0xA210)
#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
Expand Down
13 changes: 0 additions & 13 deletions drivers/gpu/drm/i915/intel_pm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7118,23 +7118,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)

static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 vd_pg_enable = 0;
unsigned int i;

/* Wa_1409120013:tgl */
I915_WRITE(ILK_DPFC_CHICKEN,
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);

/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
for (i = 0; i < I915_MAX_VCS; i++) {
if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
VDN_MFX_POWERGATE_ENABLE(i);
}

I915_WRITE(POWERGATE_ENABLE,
I915_READ(POWERGATE_ENABLE) | vd_pg_enable);

/* Wa_1409825376:tgl (pre-prod)*/
if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
Expand Down

0 comments on commit 695dc55

Please sign in to comment.