Discussions

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  About advanced C++ containers and features in XLS[cc]

  Mars-Cat2023 asked Oct 16, 2024 in Q&A · Answered

  

  

  

  

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  The mod operation is not supported when XLS_IR is converted to Z3. Is there a solution

  zhang0504 asked Oct 24, 2024 in Q&A · Unanswered

  

  

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  How to create a new delay model

  hnpl started Sep 26, 2024 in General

  

  

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  Lower function invocations to Verilog module instantiations

  joachimschmidt557 started Jun 27, 2022 in Ideas

  

  

  

  

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  Adding Formal Verification for IR

  dassbrothers started Aug 13, 2024 in Ideas · Closed

  

  

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  Chatroom

  lachlansneff started Nov 29, 2021 in General

  

  

  

  

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  Unoptimised verilog code (simple_add example)

  RohitPatil555 asked May 19, 2021 in Q&A · Closed · Unanswered

  

  

  

  

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  Ubuntu 18.04 build error

  KuiWei004 asked Mar 20, 2021 in Q&A · Closed · Unanswered

  

  

  

  

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  Why does out-of-bounds array indexing/slicing clamp to the last array value?

  documentation Improvements or additions to documentation dslx DSLX (domain specific language) implementation / front-end

  mikex-oss asked Jun 18, 2024 in Q&A · Unanswered

  

  

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  [DSLX->SystemVerilog] Output ports' names

  Muxianesty asked May 23, 2024 in Q&A · Closed · Answered

  

  

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  slice built-in function example

  pbelecky started Nov 30, 2021 in General · Closed

  

  

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  Welcome to xls Discussions!

  cdleary started Dec 10, 2020 in General

  

  

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