Skip to content

Commit

Permalink
refactor: system .params() method now gets component parameters from …
Browse files Browse the repository at this point in the history 
…._get_params() method
  • Loading branch information
@geddy11
geddy11 committed May 26, 2024
1 parent bb2f017 commit 320fc09
Show file tree
Hide file tree
Showing 3 changed files with 92 additions and 51 deletions.
8 changes: 4 additions & 4 deletions docs/nb/PCIe FPGA.ipynb
View file
Original file line number Diff line number Diff line change
Expand Up @@ -107,15 +107,15 @@
" idx = \"[{}]\".format(channel+1)\n",
" sys.add_comp(src, comp=Converter(\"ADC\"+idx+\" buck 2.3V\", vo=2.3, eff=eff_2v3))\n",
" sys.add_comp(\"ADC\"+idx+\" buck 2.3V\", comp=RLoss(\"ADC\"+idx+\" ferrit1\", rs=0.087))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit1\", comp=LinReg(\"ADC\"+idx+\" LDO 1.8V\", vo=1.8, iq=0.5, vdrop=0.15, limits={\"vo\":[1.8, 1.8]}))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit1\", comp=LinReg(\"ADC\"+idx+\" LDO 1.8V\", vo=1.8, iq=0.5e-6, vdrop=0.15, limits={\"vo\":[1.8, 1.8]}))\n",
" sys.add_comp(\"ADC\"+idx+\" LDO 1.8V\", comp=ILoad(\"ADC\"+idx+\" AVVD18\", ii=0.5))\n",
" sys.add_comp(src, comp=Converter(\"ADC\"+idx+\" buck 1.7V\", vo=1.7, eff=eff_1v7))\n",
" sys.add_comp(\"ADC\"+idx+\" buck 1.7V\", comp=RLoss(\"ADC\"+idx+\" ferrit2\", rs=0.103))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[1] 1.2V\", vo=1.2, iq=0.23, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[1] 1.2V\", vo=1.2, iq=0.23e-6, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" LDO[1] 1.2V\", comp=ILoad(\"ADC\"+idx+\" AVVD12\", ii=0.74))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[2] 1.2V\", vo=1.2, iq=0.23, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[2] 1.2V\", vo=1.2, iq=0.23e-6, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" LDO[2] 1.2V\", comp=ILoad(\"ADC\"+idx+\" CLKVDD\", ii=0.086))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[3] 1.2V\", vo=1.2, iq=0.23, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" ferrit2\", comp=LinReg(\"ADC\"+idx+\" LDO[3] 1.2V\", vo=1.2, iq=0.23e-6, vdrop=0.15, limits={\"vo\":[1.2, 1.2]}))\n",
" sys.add_comp(\"ADC\"+idx+\" LDO[3] 1.2V\", comp=ILoad(\"ADC\"+idx+\" DVDD\", ii=1.41))\n",
" return sys\n",
"\n",
Expand Down
66 changes: 66 additions & 0 deletions src/sysloss/components.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -261,6 +261,13 @@ def _solv_get_warns(self, vi, vo, ii, io, phase, phase_conf={}):
"""Check limits"""
return _get_warns(self._limits, {"ii": ii, "io": io})

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["vo"] = self._params["vo"]
ret["rs"] = self._params["rs"]
return ret


class PLoad:
"""Power load.
Expand Down Expand Up @@ -357,6 +364,13 @@ def _solv_get_warns(self, vi, vo, ii, io, phase, phase_conf={}):
return ""
return _get_warns(self._limits, {"vi": vi, "ii": ii})

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["pwr"] = self._params["pwr"]
ret["pwrs"] = self._params["pwrs"]
return ret


class ILoad(PLoad):
"""Current load.
Expand Down Expand Up @@ -422,6 +436,13 @@ def _solv_inp_curr(self, vi, vo, io, phase, phase_conf={}):

return abs(i)

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["ii"] = self._params["ii"]
ret["iis"] = self._params["iis"]
return ret


class RLoad(PLoad):
"""Resistive load.
Expand Down Expand Up @@ -479,6 +500,12 @@ def _solv_inp_curr(self, vi, vo, io, phase, phase_conf={}):
r = phase_conf[phase]
return abs(vi) / r

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["rs"] = self._params["rs"]
return ret


class RLoss:
"""Resistive loss.
Expand Down Expand Up @@ -576,6 +603,12 @@ def _solv_get_warns(self, vi, vo, ii, io, phase, phase_conf={}):
"""Check limits"""
return _get_warns(self._limits, {"vi": vi, "vo": vo, "ii": ii, "io": io})

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["rs"] = self._params["rs"]
return ret


class VLoss:
"""Voltage loss.
Expand Down Expand Up @@ -702,6 +735,15 @@ def _get_annot(self):
"{} voltage drop".format(self._params["name"]),
]

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
if isinstance(self._ipr, _Interp0d):
ret["vdrop"] = abs(self._params["vdrop"])
else:
ret["vdrop"] = "interp"
return ret


class Converter:
"""Voltage converter.
Expand Down Expand Up @@ -876,6 +918,18 @@ def _get_annot(self):
"{} efficiency for Vo={}V".format(self._params["name"], self._params["vo"]),
]

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["vo"] = self._params["vo"]
ret["iq"] = self._params["iq"]
if isinstance(self._ipr, _Interp0d):
ret["eff"] = abs(self._params["eff"])
else:
ret["eff"] = "interp"
ret["iis"] = self._params["iis"]
return ret


class LinReg:
"""Linear voltage converter.
Expand Down Expand Up @@ -1052,3 +1106,15 @@ def _get_annot(self):
self._params["name"], self._params["vo"]
),
]

def _get_params(self, pdict):
"""Return dict with component parameters"""
ret = pdict
ret["vo"] = self._params["vo"]
ret["vdrop"] = self._params["vdrop"]
if isinstance(self._ipr, _Interp0d):
ret["iq"] = abs(self._params["iq"])
else:
ret["iq"] = "interp"
ret["iis"] = self._params["iis"]
return ret
69 changes: 22 additions & 47 deletions src/sysloss/system.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -868,60 +868,35 @@ def params(self, limits: bool = False) -> pd.DataFrame:
lii, lio, lvi, lvo, pwrs = [], [], [], [], []
domain, dname = [], "none"
src_cnt = 0

for n in self._topo_nodes:
names += [self._g[n]._params["name"]]
typ += [self._g[n]._component_type.name]
if self._g[n]._component_type.name == "SOURCE":
dname = self._g[n]._params["name"]
src_cnt += 1
domain += [dname]
_vo, _vdrop, _iq, _rs, _eff, _ii, _pwr = "", "", "", "", "", "", ""
_iis, _pwrs = "", ""
if self._g[n]._component_type == _ComponentTypes.SOURCE:
_vo = self._g[n]._params["vo"]
_rs = self._g[n]._params["rs"]
elif self._g[n]._component_type == _ComponentTypes.LOAD:
if "pwr" in self._g[n]._params:
_pwr = self._g[n]._params["pwr"]
_pwrs = self._g[n]._params["pwrs"]
elif "rs" in self._g[n]._params:
_rs = self._g[n]._params["rs"]
else:
_ii = self._g[n]._params["ii"]
_iis = self._g[n]._params["iis"]
elif self._g[n]._component_type == _ComponentTypes.CONVERTER:
_vo = self._g[n]._params["vo"]
_iq = self._g[n]._params["iq"]
if isinstance(self._g[n]._ipr, _Interp0d):
_eff = self._g[n]._params["eff"]
else:
_eff = "interp"
_iis = self._g[n]._params["iis"]
elif self._g[n]._component_type == _ComponentTypes.LINREG:
_vo = self._g[n]._params["vo"]
_vdrop = self._g[n]._params["vdrop"]
if isinstance(self._g[n]._ipr, _Interp0d):
_iq = self._g[n]._params["iq"]
else:
_iq = "interp"
_iis = self._g[n]._params["iis"]
elif self._g[n]._component_type == _ComponentTypes.SLOSS:
if "rs" in self._g[n]._params:
_rs = self._g[n]._params["rs"]
else:
if isinstance(self._g[n]._ipr, _Interp0d):
_vdrop = self._g[n]._params["vdrop"]
else:
_vdrop = "interp"
vo += [_vo]
vdrop += [_vdrop]
iq += [_iq]
rs += [_rs]
eff += [_eff]
ii += [_ii]
pwr += [_pwr]
iis += [_iis]
pwrs += [_pwrs]
pdict = {
"vo": "",
"vdrop": "",
"iq": "",
"rs": "",
"eff": "",
"ii": "",
"pwr": "",
"iis": "",
"pwrs": "",
}
cparams = self._g[n]._get_params(pdict)
vo += [cparams["vo"]]
vdrop += [cparams["vdrop"]]
iq += [cparams["iq"]]
rs += [cparams["rs"]]
eff += [cparams["eff"]]
ii += [cparams["ii"]]
pwr += [cparams["pwr"]]
iis += [cparams["iis"]]
pwrs += [cparams["pwrs"]]
parent += [self._get_parent_name(n)]
if limits:
lii += [_get_opt(self._g[n]._limits, "ii", LIMITS_DEFAULT["ii"])]
Expand Down

0 comments on commit 320fc09

Please sign in to comment.