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DO NOT DELIVER: Add debug counters
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fjeremic committed Feb 28, 2019
1 parent 792db03 commit bf93d53
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Showing 8 changed files with 93 additions and 20 deletions.
14 changes: 7 additions & 7 deletions compiler/codegen/CodeGenRA.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1381,7 +1381,7 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,
// Perform the simulation for current block and accumulate into highWaterMark
//
TR_RegisterPressureSummary summary(state._gprPressure, state._fprPressure, state._vrfPressure);
if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
TR::DataType dtype = rc->getSymbolReference()->getSymbol()->getDataType();
if (dtype == TR::Int8 ||
Expand Down Expand Up @@ -1691,7 +1691,7 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,
}
}

if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
TR_BitVector HPRMasks = *self()->getGlobalRegisters(TR_hprSpill, self()->comp()->getMethodSymbol()->getLinkageConvention());
// We cannot assign an HPR if the corresponding GPR is alive.
Expand Down Expand Up @@ -2628,7 +2628,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
return;
}

if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
// 390 Highword, maybe move this below to else .hasRegister?
if (self()->isCandidateLoad(node, state))
Expand Down Expand Up @@ -2753,7 +2753,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
traceMsg(self()->comp(), " ++%s", self()->getDebug()->getName(child));
}

if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
// first time visiting this node, clear the flag
if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
Expand All @@ -2763,7 +2763,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
}
self()->simulateNodeEvaluation(node, state, summary);

if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
bool needToCheckHPR = false;
for (uint16_t i = 0; i < node->getNumChildren(); i++)
Expand Down Expand Up @@ -2802,7 +2802,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
}
else
{
if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
// first time visiting this node, clear the flag
if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
Expand Down Expand Up @@ -2831,7 +2831,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt

self()->simulateNodeEvaluation(node, state, summary);

if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
bool needToCheckHPR = false;
for (uint16_t i = 0; i < node->getNumChildren(); i++)
Expand Down
2 changes: 1 addition & 1 deletion compiler/codegen/OMRCodeGenerator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1137,7 +1137,7 @@ OMR::CodeGenerator::getNumberOfGlobalRegisters()
#ifdef TR_HOST_S390
uint16_t OMR::CodeGenerator::getNumberOfGlobalGPRs()
{
if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
return _firstGlobalHPR;
}
Expand Down
4 changes: 2 additions & 2 deletions compiler/optimizer/RegisterCandidate.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2852,7 +2852,7 @@ TR_RegisterCandidates::assign(TR::Block ** cfgBlocks, int32_t numberOfBlocks, in
TR::CodeGenerator * cg = comp()->cg();
cg->removeUnavailableRegisters(rc, blocks, availableRegisters);

if (comp()->cg()->supportsHighWordFacility() && !comp()->getOption(TR_DisableRegisterPressureSimulation))
if (comp()->cg()->supportsHighWordFacility() && !comp()->getOption(TR_DisableRegisterPressureSimulation) && !comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
if (!rc->getType().isInt8() && !rc->getType().isInt16() && !rc->getType().isInt32())
{
Expand Down Expand Up @@ -3769,7 +3769,7 @@ TR_RegisterCandidates::computeAvailableRegisters(TR_RegisterCandidate *rc, int32
while (bvi.hasMoreElements())
{
int32_t reg = bvi.getNextElement();
if (reg != parmReg)
if (reg != parmReg && (reg >= comp()->cg()->getFirstGlobalGPR() && reg <= comp()->cg()->getLastGlobalGPR()))
_liveOnEntryConflicts[reg].set(entryBlockNumber);
}
}
Expand Down
26 changes: 23 additions & 3 deletions compiler/z/codegen/OMRCodeGenerator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -549,6 +549,8 @@ OMR::Z::CodeGenerator::CodeGenerator()
TR::Compilation *comp = self()->comp();
_cgFlags = 0;

TR::DebugCounter::incStaticDebugCounter(comp, "hpr/total-compilations");

// Initialize Linkage for Code Generator
self()->initializeLinkage();

Expand Down Expand Up @@ -912,7 +914,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
// Initialize _globalGPRsPreservedAcrossCalls and _globalFPRsPreservedAcrossCalls
// We call init here because getNumberOfGlobal[FG]PRs() is initialized during the call to initialize() above.
//
if (self()->supportsHighWordFacility())
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
_globalGPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR + NUM_S390_HPR, self()->trMemory());
_globalFPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR + NUM_S390_HPR, self()->trMemory());
Expand Down Expand Up @@ -953,7 +955,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
TR_ASSERT(reg != -1, "Register pressure simulator doesn't support gaps in the global register table; reg %d must be removed", grn);
if (self()->getFirstGlobalGPR() <= grn && grn <= self()->getLastGlobalGPR())
{
if (self()->supportsHighWordFacility() && self()->getFirstGlobalHPR() <= grn)
if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit) && self()->getFirstGlobalHPR() <= grn)
{
// this is a bit tricky, we consider Global HPRs part of Global GPRs
_globalRegisterBitVectors[ TR_hprSpill ].set(grn);
Expand All @@ -976,7 +978,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
_globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
if (linkage->getIntegerArgument(reg) || linkage->getFloatArgument(reg))
{
if ((self()->supportsHighWordFacility()) && (grn >= self()->getFirstGlobalGPR() && grn <= self()->getLastGlobalGPR()))
if ((self()->supportsHighWordFacility()) && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit) && (grn >= self()->getFirstGlobalGPR() && grn <= self()->getLastGlobalGPR()))
{
TR_GlobalRegisterNumber grnHPR = self()->getFirstGlobalHPR() - self()->getFirstGlobalGPR() + grn;
_globalRegisterBitVectors[ TR_linkageSpill ].set(grnHPR);
Expand Down Expand Up @@ -2345,6 +2347,24 @@ OMR::Z::CodeGenerator::upgradeToHPRInstruction(TR::Instruction * inst)

self()->replaceInst(inst, newInst);

TR::DebugCounter::incStaticDebugCounter(self()->comp(), "hpr/upgrade");

if (srcUpgradable)
{
if (self()->machine()->findBestFreeRegister(inst, TR_GPR, srcReg) != NULL)
{
TR::DebugCounter::incStaticDebugCounter(self()->comp(), "hpr/upgrade-found-free-source-GPR");
}
}

if (targetUpgradable)
{
if (self()->machine()->findBestFreeRegister(inst, TR_GPR, targetReg) != NULL)
{
TR::DebugCounter::incStaticDebugCounter(self()->comp(), "hpr/upgrade-found-free-target-GPR");
}
}

if (self()->getDebug())
self()->getDebug()->addInstructionComment(s390NewInst, "HPR Upgraded");

Expand Down
8 changes: 4 additions & 4 deletions compiler/z/codegen/OMRLinkage.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -412,7 +412,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
// -> set means free
// Keep a list of global registers
//
if (self()->cg()->supportsHighWordFacility())
if (self()->cg()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit))
{
freeScratchable.init(TR::RealRegister::LastHPR + 1, self()->trMemory());
globalAllocatedRegisters.init(TR::RealRegister::LastHPR + 1, self()->trMemory());
Expand Down Expand Up @@ -575,7 +575,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
}

if (ai >= 0 &&
loadOpCode == TR::InstOpCode::L && self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
loadOpCode == TR::InstOpCode::L && self()->cg()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit) && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
loadOpCode = TR::InstOpCode::LFH;

if (((self()->isSmallIntParmsAlignedRight() && paramCursor->getType().isIntegral()) ||
Expand Down Expand Up @@ -923,7 +923,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
}
else
{
if (self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
if (self()->cg()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit) && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
{
cursor = generateExtendedHighWordInstruction(firstNode, self()->cg(), TR::InstOpCode::LHLR, self()->getRealRegister(REGNUM(ai)),
self()->getRealRegister(regNum), 0, (TR::Instruction *) cursor);
Expand Down Expand Up @@ -1215,7 +1215,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
switch(busyMoves[2][i1])
{
case 0: // Reg 2 Reg
if (self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(target))->isHighWordRegister())
if (self()->cg()->supportsHighWordFacility() && !self()->comp()->getOption(TR_Enable64BitRegsOn32Bit) && self()->getRealRegister(REGNUM(target))->isHighWordRegister())
{
cursor = generateExtendedHighWordInstruction(firstNode, self()->cg(), TR::InstOpCode::LHLR, self()->getRealRegister(REGNUM(target)),
self()->getRealRegister(REGNUM(source)), 0, (TR::Instruction *) cursor);
Expand Down
51 changes: 49 additions & 2 deletions compiler/z/codegen/OMRMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -148,10 +148,12 @@ OMR::Z::Machine::registerCopy(TR::CodeGenerator* cg,
TR::InstOpCode::LR;

cursor = generateRRInstruction(cg, mnemonic, node, targetReg, sourceReg, precedingInstruction);
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/GPR");
}
else
{
cursor = generateExtendedHighWordInstruction(node, cg, TR::InstOpCode::LLHFR, targetReg, sourceReg, 0, precedingInstruction);
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/HPR");
}
break;
}
Expand All @@ -164,14 +166,16 @@ OMR::Z::Machine::registerCopy(TR::CodeGenerator* cg,
TR::InstOpCode::LHHR;

cursor = generateExtendedHighWordInstruction(node, cg, mnemonic, targetReg, sourceReg, 0, precedingInstruction);
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/HPR");
break;
}
case TR_FPR:
cursor = generateRRInstruction(cg, TR::InstOpCode::LDR, node, targetReg, sourceReg, precedingInstruction);
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/FPR");
break;
case TR_VRF:
cursor = generateVRRaInstruction(cg, TR::InstOpCode::VLR, node, targetReg, sourceReg, precedingInstruction);

TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/VRF");
break;
}

Expand Down Expand Up @@ -229,6 +233,8 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
}
else
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/FPR", 3);

TR::Instruction * currentInstruction = precedingInstruction;
TR_BackingStore * location;
location = cg->allocateSpill(8, false, NULL);
Expand Down Expand Up @@ -265,6 +271,8 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
}
else
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/VRF", 3);

TR_BackingStore * location;
location = cg->allocateSpill(16, false, NULL);
TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, location->getSymbolReference(), cg);
Expand Down Expand Up @@ -358,6 +366,15 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
cg->traceRAInstruction(currentInstruction);

cg->freeSpill(location, TR::Compiler->om.sizeofReferenceAddress(), 0);

if (srcRegIsHPR || tgtRegIsHPR)
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/HPR");
}
else
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/GPR");
}
}
else
{
Expand All @@ -367,6 +384,14 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,

if (enableHighWordRA)
{
if (srcRegIsHPR || tgtRegIsHPR)
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/HPR");
}
else
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/GPR");
}
if (srcRegIsHPR != middleRegIsHPR)
{
currentInstruction =
Expand Down Expand Up @@ -418,6 +443,14 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
}
else
{
if (srcRegIsHPR || tgtRegIsHPR)
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/HPR");
}
else
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/shuffle/GPR");
}
currentInstruction =
generateRRInstruction(cg, opLoadReg, currentNode, sourceReg, middleReg, precedingInstruction);
cg->traceRAInstruction(currentInstruction);
Expand Down Expand Up @@ -3648,6 +3681,8 @@ OMR::Z::Machine::spillRegister(TR::Instruction * currentInstruction, TR::Registe
}
self()->cg()->traceRegisterAssignment("\nHW RA: HW spill: %R(%R) into %R\n", virtReg, best, freeHighWordReg);

TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/HPR/register");

// spill to HW
if (alreadySpilledToHPR)
{
Expand Down Expand Up @@ -3749,17 +3784,27 @@ OMR::Z::Machine::spillRegister(TR::Instruction * currentInstruction, TR::Registe
{
if (best->isHighWordRegister())
{
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/HPR/memory");
opCode = TR::InstOpCode::LFH;
}
else if (best->isLowWordRegister() && best->getHighWordRegister()->getAssignedRegister() != virtReg)
{
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/GPR");
opCode = TR::InstOpCode::L;
}
else
{
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/GPR");
}
//TR_ASSERTC( TR::Compiler->target.is64Bit(),comp, "\nallocateSpill has incorrect spill slot size");
//this assume kicks in for SLLG, MGHI etc on 31bit
if (debugObj)
self()->cg()->traceRegisterAssignment(" HW RA: spilling %R:%R", virtReg, best);
}
else
{
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/GPR");
}
break;
case TR_FPR:
if (!comp->getOption(TR_DisableOOL) &&
Expand All @@ -3773,13 +3818,15 @@ OMR::Z::Machine::spillRegister(TR::Instruction * currentInstruction, TR::Registe
}
else
{
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/FPR");
location = self()->cg()->allocateSpill(8, false, NULL, true); // TODO: Use 4 for single-precision values
if (debugObj)
self()->cg()->traceRegisterAssignment("\nSpilling FPR %s to (%p)\n", debugObj->getName(virtReg),location);
}
opCode = TR::InstOpCode::LD;
break;
case TR_VRF:
TR::DebugCounter::incStaticDebugCounter(comp, "hpr/spill/VRF");
// Spill of size 16 has never been done before. The call hierarchy seems to support it but this should be watched closely.
location = self()->cg()->allocateSpill(16, false, NULL, true);
if (debugObj)
Expand Down Expand Up @@ -5723,7 +5770,7 @@ OMR::Z::Machine::initializeGlobalRegisterTable()
// [2] https://github.com/eclipse/omr/blob/9d1d8cf3048781bc6d87e6a1079167586cc5aa4d/compiler/codegen/CodeGenRA.cpp#L2889-L2903
// [3] https://github.com/eclipse/omr/blob/9d1d8cf3048781bc6d87e6a1079167586cc5aa4d/compiler/z/codegen/ControlFlowEvaluator.cpp#L1098-L1102

if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableRegisterPressureSimulation))
if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableRegisterPressureSimulation) && !comp->getOption(TR_Enable64BitRegsOn32Bit))
{
// HPR
// this is a bit tricky, we consider Global HPRs part of Global GPRs
Expand Down
6 changes: 5 additions & 1 deletion compiler/z/codegen/OMRTreeEvaluator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -9802,6 +9802,7 @@ OMR::Z::TreeEvaluator::passThroughEvaluator(TR::Node * node, TR::CodeGenerator *
}
if (cg->machine()->getHPRFromGlobalRegisterNumber(node->getGlobalRegisterNumber()) != NULL)
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/gra");
copyReg->setAssignToHPR(true);
}
switch (kind)
Expand Down Expand Up @@ -12006,6 +12007,7 @@ OMR::Z::TreeEvaluator::iRegLoadEvaluator(TR::Node * node, TR::CodeGenerator * cg
globalReg->setAssignToHPR(false);
if (cg->machine()->getHPRFromGlobalRegisterNumber(globalRegNum) != NULL)
{
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/gra");
globalReg->setAssignToHPR(true);
}
}
Expand Down Expand Up @@ -12101,6 +12103,7 @@ OMR::Z::TreeEvaluator::iRegStoreEvaluator(TR::Node * node, TR::CodeGenerator * c
generateRILInstruction(cg, TR::InstOpCode::IIHF, child, globalReg, static_cast<int32_t>((getIntegralValue(child))));
child->setRegister(globalReg);
}
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/gra");
globalReg->setAssignToHPR(true);
}
else if (useHPR && child->getOpCode().isLoadVar() && child->getType().isInt32())
Expand All @@ -12114,6 +12117,7 @@ OMR::Z::TreeEvaluator::iRegStoreEvaluator(TR::Node * node, TR::CodeGenerator * c
generateRXInstruction(cg, TR::InstOpCode::LFH, child, globalReg, generateS390MemoryReference(child,cg));
child->setRegister(globalReg);
}
TR::DebugCounter::incStaticDebugCounter(cg->comp(), "hpr/gra");
globalReg->setAssignToHPR(true);
}
else
Expand Down Expand Up @@ -12141,7 +12145,7 @@ OMR::Z::TreeEvaluator::iRegStoreEvaluator(TR::Node * node, TR::CodeGenerator * c
((child->getOpCodeValue() == TR::su2i) && (child->getFirstChild()->getOpCodeValue() == TR::cloadi)) ||
((child->getOpCodeValue() == TR::l2i) && (child->getFirstChild()->getOpCodeValue() == TR::i2l));

if (cg->supportsHighWordFacility())
if (cg->supportsHighWordFacility() && !comp->getOption(TR_Enable64BitRegsOn32Bit))
{
child_sign_extended = false;
}
Expand Down
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