Functional support of Intel Sapphire Rapids #5084
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Codecov ReportAttention: Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## main #5084 +/- ##
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+ Coverage 83.15% 83.18% +0.02%
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Files 248 248
Lines 26910 26910
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+ Hits 22377 22384 +7
+ Misses 4533 4526 -7
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Reorder normalization from lower bits to higher and from EAX to EDX. No functional change. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
The CPUID notation is widely used in various Intel docs including SDM. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
The CPUID notation is widely used in various AMD docs including APM. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
There is no benefit defining constants that are used only once. Rather it makes harder to read code since the definition and usage are far apart. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
As mentioned in [1], Intel 64 Architecture x2APIC Specification has been merged into Volumes 2 and 3 of Intel 64 and IA-32 architectures software developer's manual. [1]: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
The last commit updates quotes of Intel specification from x2APIC spec to Intel SDM. In accrodance with the change, update variable names and comments (e.g. level => domain) and correct some comments appropriately. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Our supported kernels no longer return any subleaves >= 1. We inserted subleaf 1 intentionally but subleaves >= 2 are not expected there. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
The number of bits that the x2APIC ID must be shifted to the right to address instances of the socket domain, which is next higher-scoped domain to the core domain, was hardcoded as 7. That means up to 128 vcpus support. Currently the max vcpu count is hardcoded as 32, so it is enough but we might want to increase it in the future. To avoid unexpected issues when increasing the max vcpu count, calculate the value based on the max vCPU count. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Show which combination of subleaf, register and bit(s) failed to set, remove unused error variant and reorder error variants in alphabetical order. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
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Since CPUID notation uses the upper bound inclusive, use RangeInclusive instead of Range. Also, make set_range() and get_range() more readable and reliable by always validating that `y` fits within the given range and by asserting `end` is less than 32. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
EAX, EBX, ECX and EDX are the all registers returned. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Intel Sapphire Rapids has CPUID leaf 0x1F that is a preferred superset to leaf 0xB. Intel recommends using leaf 0x1F when available rather than leaf 0xB. We don't use any other domains than ones supported leaf 0xB, so just copy leaf 0xB to leaf 0x1F. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Some structs are imported in the last commit. Let's remove turbo fish! Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Intel Sapphire Rapids does not report its frequency in the model name
string on host ("Intel(R) Xeon(R) Platinum 8488C").
Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
CPUID leaf 1FH is a preferred superset to CPUID leaf 0BH. For the same reason as CPUID leaf 0BH, the subleaf 2 should be skipped if guest userspace cpuid command enumerates it. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
The MSR is R/W and guest OS modifies it after boot to control UMWAIT feature. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
MSR_IA32_XFD is R/W MSR for guest OS to control which XSAVE-enabled features are temporarily disabled. Guest OS disables TILEDATA by default using the MSR. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
CPU features that guest kernel can vary depending on its kernel version. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
Intel Sapphire Rapids has some new features compared to older Intel processors. Some of them are just not virtualized by KVM, others started to be passed through to guests since specific kernel versions, and the others can be emulated but now supported by hardware. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
REPTAR is reported "vulnerable" inside guest on Intel Sapphire Rapids for the same reason as Intel Ice Lake (microcode versio not exposed to guests). Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
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Changes
Reason
Intel Sapphire Rapids reports more CPUID leaves (0x1C - 0x1F) than Intel Ice Lake:
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[ ] I have mentioned all user-facing changes inCHANGELOG.md.[ ] If a specific issue led to this PR, this PR closes the issue.Runbook for Firecracker API changes.
integration tests.
[ ] I have linked an issue to every newTODO.rust-vmm.