030-iob18: actually find RIOB18.IOB_Y0.SSTL*.IN, reduces specimens to 40

Signed-off-by: Hans Baier <hansfbaier@gmail.com>
f4pga · Dec 15, 2022 · cf8b6c6 · cf8b6c6
1 parent 7800bcb
commit cf8b6c6
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/fuzzers/030-iob18/Makefile b/fuzzers/030-iob18/Makefile
@@ -5,7 +5,7 @@
 # https://opensource.org/licenses/ISC
 #
 # SPDX-License-Identifier: ISC
-N := 80
+N := 40
 SPECIMENS_DEPS := build/iobanks.txt
 include ../fuzzer.mk
 

diff --git a/fuzzers/030-iob18/generate.py b/fuzzers/030-iob18/generate.py
@@ -125,10 +125,14 @@ def main():
                     segmk.add_site_tag(site, 'ZIBUF_LOW_PWR', 1 ^ d['IBUF_LOW_PWR'])
 
             elif d['type'] == 'IBUFDS':
+                is_sstl = 'SSTL' in iostandard
+                is_even_sstl_site = (int(site.split("Y")[-1]) % 2 == 0) and is_sstl
                 psite = d['pair_site']
                 segmk.add_site_tag(site,  'INOUT', 0)
                 segmk.add_site_tag(site,  '{}.IN_USE'.format(iostandard), 1)
-                segmk.add_site_tag(site,  '{}.IN'.format(iostandard), 1)
+                # the bit 39_127 which marks a single ended SSTL input is not set for IN_DIFF at Y0
+                # so to avoid losing that bit we have to set .IN zero here
+                segmk.add_site_tag(site,  '{}.IN'.format(iostandard), 0 if is_even_sstl_site else 1)
                 segmk.add_site_tag(site,  '{}.IN_DIFF'.format(iostandard), 1)
                 segmk.add_site_tag(psite, '{}.IN_DIFF'.format(iostandard), 1)
                 segmk.add_site_tag(site,  '{}.OUT'.format(iostandard), 0)