build(deps): bump third_party/litex from 95b310e
to 9b8a5b6
#3458
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Bumps third_party/litex from
95b310e
to9b8a5b6
.Commits
9b8a5b6
CHANGES: Update.8c73afe
Merge pull request #1823 from trabucayre/cpuNone_config1613335
soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)eedebd8
litex/soc/cores/cpu/init, litex/soc/integration/soc: modifying CPUNone to...4b9601b
Merge pull request #1822 from trabucayre/rework_toolsa2c39a7
tools: litex_server, litex_client and remote: don't hardcode bus address5efdbd9
Merge pull request #1821 from trabucayre/uartbone_add_width321254c
soc/integration/soc: pass bus.address_width to UARTBone constructorf06ef52
soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor9374196
soc/cores/uart: allows 64bits in Stream2WishboneDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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