SPI: Clear DMA interrupts before (not after) DMA starts

esp-hal/CHANGELOG.md

@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Improve error detection in the I2C driver (#1847)
 - Fix I2S async-tx (#1833)
 - Fix PARL_IO async-rx (#1851)
+- SPI: Clear DMA interrupts before (not after) DMA starts (#1859)
 
 ### Removed
 

esp-hal/src/otg_fs.rs

@@ -176,6 +176,7 @@ pub mod asynch {
         ///
         /// * `ep_out_buffer` - An internal buffer used to temporarily store
         ///   received packets.
+        ///
         /// Must be large enough to fit all OUT endpoint max packet sizes.
         /// Endpoint allocation will fail if it is too small.
         pub fn new(_peri: Usb<'d>, ep_out_buffer: &'d mut [u8], config: Config) -> Self {

esp-hal/src/soc/esp32/gpio.rs

@@ -41,6 +41,7 @@
 //! two different banks:
 //!   * `InterruptStatusRegisterAccessBank0`
 //!   * `InterruptStatusRegisterAccessBank1`.
+//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.

esp-hal/src/soc/esp32s2/gpio.rs

@@ -48,6 +48,7 @@
 //! two different banks:
 //!   * `InterruptStatusRegisterAccessBank0`
 //!   * `InterruptStatusRegisterAccessBank1`.
+//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.

esp-hal/src/soc/esp32s3/gpio.rs

@@ -36,6 +36,7 @@
 //! two different banks:
 //!   * `InterruptStatusRegisterAccessBank0`
 //!   * `InterruptStatusRegisterAccessBank1`.
+//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.

esp-hal/src/spi/master.rs

@@ -2036,14 +2036,14 @@ where
         self.update();
 
         reset_dma_before_load_dma_dscr(reg_block);
+        self.clear_dma_interrupts();
         tx_chain.fill_for_tx(false, write_buffer_ptr, write_buffer_len)?;
         tx.prepare_transfer_without_start(self.dma_peripheral(), tx_chain)
             .and_then(|_| tx.start_transfer())?;
         rx_chain.fill_for_rx(false, read_buffer_ptr, read_buffer_len)?;
         rx.prepare_transfer_without_start(self.dma_peripheral(), rx_chain)
             .and_then(|_| rx.start_transfer())?;
 
-        self.clear_dma_interrupts();
         reset_dma_before_usr_cmd(reg_block);
 
         reg_block.cmd().modify(|_, w| w.usr().set_bit());
@@ -2086,13 +2086,13 @@ where
         self.update();
 
         reset_dma_before_load_dma_dscr(reg_block);
+        self.clear_dma_interrupts();
         chain.fill_for_tx(false, ptr, len)?;
         unsafe {
             tx.prepare_transfer_without_start(self.dma_peripheral(), chain)
                 .and_then(|_| tx.start_transfer())?;
         }
 
-        self.clear_dma_interrupts();
         reset_dma_before_usr_cmd(reg_block);
 
         reg_block.cmd().modify(|_, w| w.usr().set_bit());
@@ -2117,11 +2117,11 @@ where
         self.update();
 
         reset_dma_before_load_dma_dscr(reg_block);
+        self.clear_dma_interrupts();
         chain.fill_for_rx(false, ptr, len)?;
         rx.prepare_transfer_without_start(self.dma_peripheral(), chain)
             .and_then(|_| rx.start_transfer())?;
 
-        self.clear_dma_interrupts();
         reset_dma_before_usr_cmd(reg_block);
 
         reg_block.cmd().modify(|_, w| w.usr().set_bit());