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Small fixes + exclude downgrade and drop for esp32c6
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Downgrade for `esp32c6` is not implemented so far
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@playfulFence
playfulFence committed Jul 2, 2024
1 parent 878c859 commit c23d46f
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Showing 2 changed files with 54 additions and 65 deletions.
14 changes: 8 additions & 6 deletions esp-hal/src/rng.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -147,9 +147,7 @@ impl rand_core::RngCore for Rng {
/// let mut trng = Trng::new(peripherals.RNG, &mut peripherals.ADC1);
/// trng.read(&mut buf);
/// let mut true_rand = trng.random();
///
/// let mut rng = trng.downgrade();
///
#[cfg_attr(not(esp32c6), doc = "let mut rng = trng.downgrade();")]
/// // ADC is available now
#[cfg_attr(esp32, doc = "let analog_pin = io.pins.gpio32;")]
#[cfg_attr(not(esp32), doc = "let analog_pin = io.pins.gpio3;")]
Expand All @@ -158,9 +156,8 @@ impl rand_core::RngCore for Rng {
/// Attenuation::Attenuation11dB); let mut adc1 =
/// Adc::<ADC1>::new(peripherals.ADC1, adc1_config); let pin_value: u16 =
/// nb::block!(adc1.read_oneshot(&mut adc1_pin)).unwrap();
///
/// rng.read(&mut buf);
/// true_rand = rng.random();
#[cfg_attr(not(esp32c6), doc = "rng.read(&mut buf);")]
#[cfg_attr(not(esp32c6), doc = "true_rand = rng.random();")]
/// let pin_value: u16 = nb::block!(adc1.read_oneshot(&mut adc1_pin)).unwrap();
/// # }
/// ```
Expand Down Expand Up @@ -206,10 +203,15 @@ impl<'d> Trng<'d> {

/// Downgrades the `Trng` instance to a `Rng` instance and releases the
/// ADC1.
/// For esp32c6 - blocked on https://github.com/espressif/esp-idf/issues/14124
#[cfg(not(esp32c6))]
pub fn downgrade(self) -> Rng {
self.rng
}
}

/// For esp32c6 - blocked on https://github.com/espressif/esp-idf/issues/14124
#[cfg(not(esp32c6))]
impl<'d> Drop for Trng<'d> {
fn drop(&mut self) {
crate::soc::trng::revert_trng();
Expand Down
105 changes: 46 additions & 59 deletions esp-hal/src/soc/esp32c6/trng.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,13 @@ const REGI2C_DIG_REG: u8 = 0x6d;
const REGI2C_ULP_CAL: u8 = 0x61;
const REGI2C_SAR_I2C: u8 = 0x69;

const REGI2C_BBPLL_DEVICE_EN: u32 = 1 << 5;
const REGI2C_BIAS_DEVICE_EN: u32 = 1 << 4;
const REGI2C_DIG_REG_DEVICE_EN: u32 = 1 << 8;
const REGI2C_ULP_CAL_DEVICE_EN: u32 = 1 << 6;
const REGI2C_SAR_I2C_DEVICE_EN: u32 = 1 << 7;
const I2C_MST_ANA_CONF1_M: u32 = 0x00FFFFFF;
const REGI2C_BBPLL_RD_MASK: u32 = !(1 << 7) & I2C_MST_ANA_CONF1_M;
const REGI2C_BIAS_RD_MASK: u32 = !(1 << 6) & I2C_MST_ANA_CONF1_M;
const REGI2C_DIG_REG_RD_MASK: u32 = !(1 << 10) & I2C_MST_ANA_CONF1_M;
const REGI2C_ULP_CAL_RD_MASK: u32 = !(1 << 8) & I2C_MST_ANA_CONF1_M;
const REGI2C_SAR_I2C_RD_MASK: u32 = !(1 << 9) & I2C_MST_ANA_CONF1_M;

const REGI2C_RTC_SLAVE_ID_V: u8 = 0xFF;
const REGI2C_RTC_SLAVE_ID_S: u8 = 0;
const REGI2C_RTC_ADDR_V: u8 = 0xFF;
Expand Down Expand Up @@ -122,9 +124,9 @@ pub(crate) fn ensure_randomness() {
regi2c_write_mask(
I2C_SAR_ADC,
I2C_SAR_ADC_HOSTID,
ADC_SARADC1_ENCAL_REF_ADDR,
ADC_SARADC1_ENCAL_REF_ADDR_MSB,
ADC_SARADC1_ENCAL_REF_ADDR_LSB,
ADC_SARADC2_ENCAL_REF_ADDR,
ADC_SARADC2_ENCAL_REF_ADDR_MSB,
ADC_SARADC2_ENCAL_REF_ADDR_LSB,
1,
);

Expand All @@ -134,7 +136,7 @@ pub(crate) fn ensure_randomness() {
ADC_SAR2_INITIAL_CODE_HIGH_ADDR,
ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB,
ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB,
0x60,
0x08,
);

regi2c_write_mask(
Expand Down Expand Up @@ -188,6 +190,7 @@ pub(crate) fn ensure_randomness() {
}
}

#[allow(unused)]
pub(crate) fn revert_trng() {
let apb_saradc = unsafe { &*crate::peripherals::APB_SARADC::ptr() };
let pmu = unsafe { &*crate::peripherals::PMU::ptr() };
Expand Down Expand Up @@ -287,49 +290,43 @@ fn regi2c_enable_block(block: u8) {
.clk_conf()
.modify(|_, w| w.clk_i2c_mst_en().set_bit());

modem_lpcon
.i2c_mst_clk_conf()
.modify(|_, w| w.clk_i2c_mst_sel_160m().set_bit());

lp_i2c_ana
.date()
.modify(|_, w| w.lp_i2c_ana_mast_i2c_mat_clk_en().set_bit());

match block {
REGI2C_BBPLL => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 | REGI2C_BBPLL_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() | REGI2C_BBPLL_RD_MASK)
});
}
REGI2C_BIAS => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 | REGI2C_BIAS_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() | REGI2C_BIAS_RD_MASK)
});
}
REGI2C_DIG_REG => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 | REGI2C_DIG_REG_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() | REGI2C_DIG_REG_RD_MASK)
});
}
REGI2C_ULP_CAL => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 | REGI2C_ULP_CAL_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() | REGI2C_ULP_CAL_RD_MASK)
});
}
REGI2C_SAR_I2C => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 | REGI2C_SAR_I2C_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() | REGI2C_SAR_I2C_RD_MASK)
});
}
_ => (),
Expand All @@ -343,43 +340,33 @@ fn regi2c_disable_block(block: u8) {
unsafe {
match block {
REGI2C_BBPLL => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 & !REGI2C_BBPLL_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() & !REGI2C_BBPLL_RD_MASK)
});
}
REGI2C_BIAS => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32 & !REGI2C_BIAS_DEVICE_EN)
as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() & !REGI2C_BIAS_RD_MASK)
});
}
REGI2C_DIG_REG => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32
& !REGI2C_DIG_REG_DEVICE_EN) as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() & !REGI2C_DIG_REG_RD_MASK)
});
}
REGI2C_ULP_CAL => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32
& !REGI2C_ULP_CAL_DEVICE_EN) as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() & !REGI2C_ULP_CAL_RD_MASK)
});
}
REGI2C_SAR_I2C => {
lp_i2c_ana.device_en().modify(|r, w| {
w.lp_i2c_ana_mast_i2c_device_en().bits(
(r.lp_i2c_ana_mast_i2c_device_en().bits() as u32
& !REGI2C_SAR_I2C_DEVICE_EN) as u16,
)
lp_i2c_ana.ana_conf1().modify(|r, w| {
w.lp_i2c_ana_mast_ana_conf1()
.bits(r.lp_i2c_ana_mast_ana_conf1().bits() & !REGI2C_SAR_I2C_RD_MASK)
});
}
_ => (),
Expand Down

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